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[soc.git] / src / soc / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
15 """
16
17 import os, sys
18 from collections import OrderedDict
19
20 from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
21 SV64P_PID_SIZE, SVP64RMFields,
22 SVP64RM_EXTRA2_SPEC_SIZE,
23 SVP64RM_EXTRA3_SPEC_SIZE,
24 SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
25 SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
26 SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
27 SVP64RM_ELWIDTH_SIZE)
28 from soc.decoder.pseudo.pagereader import ISA
29 from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
30 from soc.decoder.selectable_int import SelectableInt
31
32
33 # decode GPR into sv extra
34 def get_extra_gpr(etype, regmode, field):
35 if regmode == 'scalar':
36 # cut into 2-bits 5-bits SS FFFFF
37 sv_extra = field >> 5
38 field = field & 0b11111
39 else:
40 # cut into 5-bits 2-bits FFFFF SS
41 sv_extra = field & 0b11
42 field = field >> 2
43 return sv_extra, field
44
45
46 # decode 3-bit CR into sv extra
47 def get_extra_cr_3bit(etype, regmode, field):
48 if regmode == 'scalar':
49 # cut into 2-bits 3-bits SS FFF
50 sv_extra = field >> 3
51 field = field & 0b111
52 else:
53 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
54 sv_extra = field & 0b1111
55 field = field >> 4
56 return sv_extra, field
57
58
59 # decodes SUBVL
60 def decode_subvl(encoding):
61 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
62 assert encoding in pmap, \
63 "encoding %s for SUBVL not recognised" % encoding
64 return pmap[encoding]
65
66
67 # decodes elwidth
68 def decode_elwidth(encoding):
69 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
70 assert encoding in pmap, \
71 "encoding %s for elwidth not recognised" % encoding
72 return pmap[encoding]
73
74
75 # decodes predicate register encoding
76 def decode_predicate(encoding):
77 pmap = { # integer
78 '1<<r3': (0, 0b001),
79 'r3' : (0, 0b010),
80 '~r3' : (0, 0b011),
81 'r10' : (0, 0b100),
82 '~r10' : (0, 0b101),
83 'r30' : (0, 0b110),
84 '~r30' : (0, 0b111),
85 # CR
86 'lt' : (1, 0b000),
87 'nl' : (1, 0b001), 'ge' : (1, 0b001), # same value
88 'gt' : (1, 0b010),
89 'ng' : (1, 0b011), 'le' : (1, 0b011), # same value
90 'eq' : (1, 0b100),
91 'ne' : (1, 0b101),
92 'so' : (1, 0b110), 'un' : (1, 0b110), # same value
93 'ns' : (1, 0b111), 'nu' : (1, 0b111), # same value
94 }
95 assert encoding in pmap, \
96 "encoding %s for predicate not recognised" % encoding
97 return pmap[encoding]
98
99
100 # decodes "Mode" in similar way to BO field (supposed to, anyway)
101 def decode_bo(encoding):
102 pmap = { # TODO: double-check that these are the same as Branch BO
103 'lt' : 0b000,
104 'nl' : 0b001, 'ge' : 0b001, # same value
105 'gt' : 0b010,
106 'ng' : 0b011, 'le' : 0b011, # same value
107 'eq' : 0b100,
108 'ne' : 0b101,
109 'so' : 0b110, 'un' : 0b110, # same value
110 'ns' : 0b111, 'nu' : 0b111, # same value
111 }
112 assert encoding in pmap, \
113 "encoding %s for BO Mode not recognised" % encoding
114 return pmap[encoding]
115
116 # partial-decode fail-first mode
117 def decode_ffirst(encoding):
118 if encoding in ['RC1', '~RC1']:
119 return encoding
120 return decode_bo(encoding)
121
122
123 def decode_reg(field):
124 # decode the field number. "5.v" or "3.s" or "9"
125 field = field.split(".")
126 regmode = 'scalar' # default
127 if len(field) == 2:
128 if field[1] == 's':
129 regmode = 'scalar'
130 elif field[1] == 'v':
131 regmode = 'vector'
132 field = int(field[0]) # actual register number
133 return field, regmode
134
135
136 def decode_imm(field):
137 ldst_imm = "(" in field and field[-1] == ')'
138 if ldst_imm:
139 return field[:-1].split("(")
140 else:
141 return None, field
142
143 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
144 class SVP64Asm:
145 def __init__(self, lst):
146 self.lst = lst
147 self.trans = self.translate(lst)
148
149 def __iter__(self):
150 yield from self.trans
151
152 def translate(self, lst):
153 isa = ISA() # reads the v3.0B pseudo-code markdown files
154 svp64 = SVP64RM() # reads the svp64 Remap entries for registers
155 for insn in lst:
156 # find first space, to get opcode
157 ls = insn.split(' ')
158 opcode = ls[0]
159 # now find opcode fields
160 fields = ''.join(ls[1:]).split(',')
161 fields = list(map(str.strip, fields))
162 print ("opcode, fields", ls, opcode, fields)
163
164 # identify if is a svp64 mnemonic
165 if not opcode.startswith('sv.'):
166 yield insn # unaltered
167 continue
168 opcode = opcode[3:] # strip leading "sv."
169
170 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
171 opmodes = opcode.split("/") # split at "/"
172 v30b_op = opmodes.pop(0) # first is the v3.0B
173 # check instruction ends with dot
174 rc_mode = v30b_op.endswith('.')
175 if rc_mode:
176 v30b_op = v30b_op[:-1]
177
178 if v30b_op not in isa.instr:
179 raise Exception("opcode %s of '%s' not supported" % \
180 (v30b_op, insn))
181 if v30b_op not in svp64.instrs:
182 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
183 (v30b_op, insn))
184 v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
185 rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
186 print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
187 print ("v3.0B regs", opcode, v30b_regs)
188 print (rm)
189
190 # right. the first thing to do is identify the ordering of
191 # the registers, by name. the EXTRA2/3 ordering is in
192 # rm['0']..rm['3'] but those fields contain the names RA, BB
193 # etc. we have to read the pseudocode to understand which
194 # reg is which in our instruction. sigh.
195
196 # first turn the svp64 rm into a "by name" dict, recording
197 # which position in the RM EXTRA it goes into
198 # also: record if the src or dest was a CR, for sanity-checking
199 # (elwidth overrides on CRs are banned)
200 decode = decode_extra(rm)
201 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
202 svp64_reg_byname = {}
203 svp64_reg_byname.update(svp64_src)
204 svp64_reg_byname.update(svp64_dest)
205
206 print ("EXTRA field index, by regname", svp64_reg_byname)
207
208 # okaaay now we identify the field value (opcode N,N,N) with
209 # the pseudo-code info (opcode RT, RA, RB)
210 assert len(fields) == len(v30b_regs), \
211 "length of fields %s must match insn `%s`" % \
212 (str(v30b_regs), insn)
213 opregfields = zip(fields, v30b_regs) # err that was easy
214
215 # now for each of those find its place in the EXTRA encoding
216 extras = OrderedDict()
217 for idx, (field, regname) in enumerate(opregfields):
218 imm, regname = decode_imm(regname)
219 extra = svp64_reg_byname.get(regname, None)
220 rtype = get_regtype(regname)
221 extras[extra] = (idx, field, regname, rtype, imm)
222 print (" ", extra, extras[extra])
223
224 # great! got the extra fields in their associated positions:
225 # also we know the register type. now to create the EXTRA encodings
226 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
227 ptype = rm['Ptype'] # Predication type: Twin / Single
228 extra_bits = 0
229 v30b_newfields = []
230 for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
231 # is it a field we don't alter/examine? if so just put it
232 # into newfields
233 if rtype is None:
234 v30b_newfields.append(field)
235
236 # identify if this is a ld/st immediate(reg) thing
237 ldst_imm = "(" in field and field[-1] == ')'
238 if ldst_imm:
239 immed, field = field[:-1].split("(")
240
241 field, regmode = decode_reg(field)
242 print (" ", extra_idx, rname, rtype,
243 regmode, iname, field, end=" ")
244
245 # see Mode field https://libre-soc.org/openpower/sv/svp64/
246 # XXX TODO: the following is a bit of a laborious repeated
247 # mess, which could (and should) easily be parameterised.
248 # XXX also TODO: the LD/ST modes which are different
249 # https://libre-soc.org/openpower/sv/ldst/
250
251 # encode SV-GPR field into extra, v3.0field
252 if rtype == 'GPR':
253 sv_extra, field = get_extra_gpr(etype, regmode, field)
254 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
255 # (and shrink to a single bit if ok)
256 if etype == 'EXTRA2':
257 if regmode == 'scalar':
258 # range is r0-r63 in increments of 1
259 assert (sv_extra >> 1) == 0, \
260 "scalar GPR %s cannot fit into EXTRA2 %s" % \
261 (rname, str(extras[extra_idx]))
262 # all good: encode as scalar
263 sv_extra = sv_extra & 0b01
264 else:
265 # range is r0-r127 in increments of 4
266 assert sv_extra & 0b01 == 0, \
267 "vector field %s cannot fit into EXTRA2 %s" % \
268 (rname, str(extras[extra_idx]))
269 # all good: encode as vector (bit 2 set)
270 sv_extra = 0b10 | (sv_extra >> 1)
271 elif regmode == 'vector':
272 # EXTRA3 vector bit needs marking
273 sv_extra |= 0b100
274
275 # encode SV-CR 3-bit field into extra, v3.0field
276 elif rtype == 'CR_3bit':
277 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
278 # now sanity-check (and shrink afterwards)
279 if etype == 'EXTRA2':
280 if regmode == 'scalar':
281 # range is CR0-CR15 in increments of 1
282 assert (sv_extra >> 1) == 0, \
283 "scalar CR %s cannot fit into EXTRA2 %s" % \
284 (rname, str(extras[extra_idx]))
285 # all good: encode as scalar
286 sv_extra = sv_extra & 0b01
287 else:
288 # range is CR0-CR127 in increments of 16
289 assert sv_extra & 0b111 == 0, \
290 "vector CR %s cannot fit into EXTRA2 %s" % \
291 (rname, str(extras[extra_idx]))
292 # all good: encode as vector (bit 2 set)
293 sv_extra = 0b10 | (sv_extra >> 3)
294 else:
295 if regmode == 'scalar':
296 # range is CR0-CR31 in increments of 1
297 assert (sv_extra >> 2) == 0, \
298 "scalar CR %s cannot fit into EXTRA2 %s" % \
299 (rname, str(extras[extra_idx]))
300 # all good: encode as scalar
301 sv_extra = sv_extra & 0b11
302 else:
303 # range is CR0-CR127 in increments of 8
304 assert sv_extra & 0b11 == 0, \
305 "vector CR %s cannot fit into EXTRA2 %s" % \
306 (rname, str(extras[extra_idx]))
307 # all good: encode as vector (bit 3 set)
308 sv_extra = 0b100 | (sv_extra >> 2)
309
310 # encode SV-CR 5-bit field into extra, v3.0field
311 # *sigh* this is the same as 3-bit except the 2 LSBs are
312 # passed through
313 elif rtype == 'CR_5bit':
314 cr_subfield = field & 0b11
315 field = field >> 2 # strip bottom 2 bits
316 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
317 # now sanity-check (and shrink afterwards)
318 if etype == 'EXTRA2':
319 if regmode == 'scalar':
320 # range is CR0-CR15 in increments of 1
321 assert (sv_extra >> 1) == 0, \
322 "scalar CR %s cannot fit into EXTRA2 %s" % \
323 (rname, str(extras[extra_idx]))
324 # all good: encode as scalar
325 sv_extra = sv_extra & 0b01
326 else:
327 # range is CR0-CR127 in increments of 16
328 assert sv_extra & 0b111 == 0, \
329 "vector CR %s cannot fit into EXTRA2 %s" % \
330 (rname, str(extras[extra_idx]))
331 # all good: encode as vector (bit 2 set)
332 sv_extra = 0b10 | (sv_extra >> 3)
333 else:
334 if regmode == 'scalar':
335 # range is CR0-CR31 in increments of 1
336 assert (sv_extra >> 2) == 0, \
337 "scalar CR %s cannot fit into EXTRA2 %s" % \
338 (rname, str(extras[extra_idx]))
339 # all good: encode as scalar
340 sv_extra = sv_extra & 0b11
341 else:
342 # range is CR0-CR127 in increments of 8
343 assert sv_extra & 0b11 == 0, \
344 "vector CR %s cannot fit into EXTRA2 %s" % \
345 (rname, str(extras[extra_idx]))
346 # all good: encode as vector (bit 3 set)
347 sv_extra = 0b100 | (sv_extra >> 2)
348
349 # reconstruct the actual 5-bit CR field
350 field = (field << 2) | cr_subfield
351
352 # capture the extra field info
353 print ("=>", "%5s" % bin(sv_extra), field)
354 extras[extra_idx] = sv_extra
355
356 # append altered field value to v3.0b, differs for LDST
357 if ldst_imm:
358 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
359 else:
360 v30b_newfields.append(str(field))
361
362 print ("new v3.0B fields", v30b_op, v30b_newfields)
363 print ("extras", extras)
364
365 # rright. now we have all the info. start creating SVP64 RM
366 svp64_rm = SVP64RMFields()
367
368 # begin with EXTRA fields
369 for idx, sv_extra in extras.items():
370 if idx is None: continue
371 if etype == 'EXTRA2':
372 svp64_rm.extra2[idx].eq(
373 SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
374 else:
375 svp64_rm.extra3[idx].eq(
376 SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
377
378 # parts of svp64_rm
379 mmode = 0 # bit 0
380 pmask = 0 # bits 1-3
381 destwid = 0 # bits 4-5
382 srcwid = 0 # bits 6-7
383 subvl = 0 # bits 8-9
384 smask = 0 # bits 16-18 but only for twin-predication
385 mode = 0 # bits 19-23
386
387 has_pmask = False
388 has_smask = False
389
390 saturation = None
391 src_zero = 0
392 dst_zero = 0
393 sv_mode = None
394
395 mapreduce = False
396 mapreduce_crm = False
397 mapreduce_svm = False
398
399 predresult = False
400 failfirst = False
401
402 # ok let's start identifying opcode augmentation fields
403 for encmode in opmodes:
404 # predicate mask (dest)
405 if encmode.startswith("m="):
406 pme = encmode
407 pmmode, pmask = decode_predicate(encmode[2:])
408 mmode = pmmode
409 has_pmask = True
410 # predicate mask (src, twin-pred)
411 elif encmode.startswith("sm="):
412 sme = encmode
413 smmode, smask = decode_predicate(encmode[3:])
414 mmode = smmode
415 has_smask = True
416 # vec2/3/4
417 elif encmode.startswith("vec"):
418 subvl = decode_subvl(encmode[3:])
419 # elwidth
420 elif encmode.startswith("ew="):
421 destwid = decode_elwidth(encmode[3:])
422 elif encmode.startswith("sw="):
423 srcwid = decode_elwidth(encmode[3:])
424 # saturation
425 elif encmode == 'sats':
426 assert sv_mode is None
427 saturation = 1
428 sv_mode = 0b10
429 elif encmode == 'satu':
430 assert sv_mode is None
431 sv_mode = 0b10
432 saturation = 0
433 # predicate zeroing
434 elif encmode == 'sz':
435 src_zero = 1
436 elif encmode == 'dz':
437 dst_zero = 1
438 # failfirst
439 elif encmode.startswith("ff="):
440 assert sv_mode is None
441 sv_mode = 0b01
442 failfirst = decode_ffirst(encmode[3:])
443 # predicate-result, interestingly same as fail-first
444 elif encmode.startswith("pr="):
445 assert sv_mode is None
446 sv_mode = 0b11
447 predresult = decode_ffirst(encmode[3:])
448 # map-reduce mode
449 elif encmode == 'mr':
450 assert sv_mode is None
451 sv_mode = 0b00
452 mapreduce = True
453 elif encmode == 'crm': # CR on map-reduce
454 assert sv_mode is None
455 sv_mode = 0b00
456 mapreduce_crm = True
457 elif encmode == 'svm': # sub-vector mode
458 mapreduce_svm = True
459
460 # sanity-check that 2Pred mask is same mode
461 if has_pmask and has_smask:
462 assert smmode == pmmode, \
463 "predicate masks %s and %s must be same reg type" % \
464 (pme, sme)
465
466 # sanity-check that twin-predication mask only specified in 2P mode
467 if ptype == '1P':
468 assert has_smask == False, \
469 "source-mask can only be specified on Twin-predicate ops"
470
471 # construct the mode field, doing sanity-checking along the way
472
473 if mapreduce_svm:
474 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
475 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
476
477 if src_zero:
478 assert has_smask, "src zeroing requires a source predicate"
479 if dst_zero:
480 assert has_pmask, "dest zeroing requires a dest predicate"
481
482 # "normal" mode
483 if sv_mode is None:
484 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
485 sv_mode = 0b00
486
487 # "mapreduce" modes
488 elif sv_mode == 0b00:
489 mode |= (0b1<<2) # sets mapreduce
490 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
491 if mapreduce_crm:
492 mode |= (0b1<<4) # sets CRM mode
493 assert rc_mode, "CRM only allowed when Rc=1"
494 # bit of weird encoding to jam zero-pred or SVM mode in.
495 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
496 if subvl == 0:
497 mode |= (src_zero << 3) # predicate src-zeroing
498 elif mapreduce_svm:
499 mode |= (1 << 3) # SVM mode
500
501 # "failfirst" modes
502 elif sv_mode == 0b01:
503 assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
504 if failfirst == 'RC1':
505 mode |= (0b1<<4) # sets RC1 mode
506 mode |= (src_zero << 3) # predicate src-zeroing
507 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
508 elif failfirst == '~RC1':
509 mode |= (0b1<<4) # sets RC1 mode...
510 mode |= (src_zero << 3) # predicate src-zeroing
511 mode |= (0b1<<2) # ... with inversion
512 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
513 else:
514 assert src_zero == 0, "src-zero not allowed in ffirst BO"
515 assert rc_mode, "ffirst BO only possible when Rc=1"
516 mode |= (failfirst << 2) # set BO
517
518 # "saturation" modes
519 elif sv_mode == 0b10:
520 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
521 mode |= (saturation<<2) # sets signed/unsigned saturation
522
523 # "predicate-result" modes. err... code-duplication from ffirst
524 elif sv_mode == 0b11:
525 assert dst_zero == 0, "dest-zero not allowed in predresult mode"
526 if predresult == 'RC1':
527 mode |= (0b1<<4) # sets RC1 mode
528 mode |= (src_zero << 3) # predicate src-zeroing
529 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
530 elif predresult == '~RC1':
531 mode |= (0b1<<4) # sets RC1 mode...
532 mode |= (src_zero << 3) # predicate src-zeroing
533 mode |= (0b1<<2) # ... with inversion
534 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
535 else:
536 assert src_zero == 0, "src-zero not allowed in pr-mode BO"
537 assert rc_mode, "pr-mode BO only possible when Rc=1"
538 mode |= (predresult << 2) # set BO
539
540 # whewww.... modes all done :)
541 # now put into svp64_rm
542 mode |= sv_mode
543 # mode: bits 19-23
544 svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
545
546 # put in predicate masks into svp64_rm
547 if ptype == '2P':
548 # source pred: bits 16-18
549 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
550 # mask mode: bit 0
551 svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
552 # 1-pred: bits 1-3
553 svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
554
555 # and subvl: bits 8-9
556 svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
557
558 # put in elwidths
559 # srcwid: bits 6-7
560 svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
561 # destwid: bits 4-5
562 svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
563
564 # nice debug printout. (and now for something completely different)
565 # https://youtu.be/u0WOIwlXE9g?t=146
566 svp64_rm_value = svp64_rm.spr.value
567 print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
568 print (" mmode 0 :", bin(mmode))
569 print (" pmask 1-3 :", bin(pmask))
570 print (" dstwid 4-5 :", bin(destwid))
571 print (" srcwid 6-7 :", bin(srcwid))
572 print (" subvl 8-9 :", bin(subvl))
573 print (" mode 19-23:", bin(mode))
574 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
575 for idx, sv_extra in extras.items():
576 if idx is None: continue
577 start = (10+idx*offs)
578 end = start + offs-1
579 print (" extra%d %2d-%2d:" % (idx, start, end),
580 bin(sv_extra))
581 if ptype == '2P':
582 print (" smask 16-17:", bin(smask))
583 print ()
584
585 # first, construct the prefix from its subfields
586 svp64_prefix = SVP64PrefixFields()
587 svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
588 svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
589 svp64_prefix.rm.eq(svp64_rm.spr)
590
591 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
592 rc = '.' if rc_mode else ''
593 yield ".long 0x%x" % svp64_prefix.insn.value
594 yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
595 print ("new v3.0B fields", v30b_op, v30b_newfields)
596
597 if __name__ == '__main__':
598 lst = ['slw 3, 1, 4',
599 'extsw 5, 3',
600 'sv.extsw 5, 3',
601 'sv.cmpi 5, 1, 3, 2',
602 'sv.setb 5, 31',
603 'sv.isel 64.v, 3, 2, 65.v',
604 'sv.setb/m=r3/sm=1<<r3 5, 31',
605 'sv.setb/vec2 5, 31',
606 'sv.setb/sw=8/ew=16 5, 31',
607 'sv.extsw./ff=eq 5, 31',
608 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
609 'sv.extsw./pr=eq 5.v, 31',
610 'sv.add. 5.v, 2.v, 1.v',
611 ]
612 lst += [
613 'sv.stw 5.v, 4(1.v)',
614 'sv.ld 5.v, 4(1.v)',
615 ]
616 isa = SVP64Asm(lst)
617 print ("list", list(isa))
618 csvs = SVP64RM()