src/spec/interfaces.py

   1 #!/usr/bin/env python
   2
   3 class Pinouts(object):
   4     def __init__(self):
   5         self.pins = {}
   6         self.fnspec = {}
   7
   8     def has_key(self, k):
   9         return self.pins.has_key(k)
  10
  11     def add_spec(self, k, v):
  12         self.fnspec[k] = v
  13
  14     def update(self, pinidx, v):
  15         if not self.pins.has_key(pinidx):
  16             self.pins[pinidx] = v
  17         else:
  18             self.pins[pinidx].update(v)
  19
  20     def keys(self):
  21         return self.pins.keys()
  22
  23     def items(self):
  24         return self.pins.items()
  25
  26     def get(self, k):
  27         return self.pins[k]
  28
  29     def __len__(self):
  30         return len(self.pins)
  31
  32     def __delitem__(self, k):
  33         del self.pins[k]
  34
  35
  36 class Pins(object):
  37
  38     def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
  39              spec=None, limit=None, origsuffix=None):
  40
  41         # function type can be in, out or inout, represented by - + *
  42         # strip function type out of each pin name
  43         self.fntype = {}
  44         for i in range(len(pingroup)):
  45             pname = pingroup[i]
  46             if not pname:
  47                 continue
  48             fntype = pname[-1]
  49             if fntype not in '+-*':
  50                 continue
  51             pname = pname[:-1]
  52             fntype = {'-': 'in', '+': 'out', '*': 'inout'}[fntype]
  53             self.fntype[pname] = fntype
  54             pingroup[i] = pname
  55
  56         self.fname = fname
  57         self.pingroup = pingroup
  58         self.bankspec = bankspec
  59         self.suffix = suffix
  60         self.origsuffix = origsuffix or suffix
  61         self.bank = bank
  62         self.mux = mux
  63
  64         # create consistent name suffixes
  65         pingroup = namesuffix(fname, suffix, pingroup)
  66         suffix = '' # hack
  67
  68         res = {}
  69         names = {}
  70         idx = 0
  71         for name in pingroup[:limit]:
  72             if suffix and name:
  73                 name_ = "%s_%s" % (name, suffix)
  74             else:
  75                 name_ = name
  76             if spec and spec.has_key(name):
  77                 continue
  78             pin = {mux: (name_, bank)}
  79             offs_bank, offs_ = offs
  80             idx_ = offs_ + idx
  81             idx += 1
  82             idx_ += bankspec[bank]
  83             res[idx_] = pin
  84             names[name] = idx_
  85         for name in pingroup:
  86             if suffix and name:
  87                 name_ = "%s_%s" % (name, suffix)
  88             else:
  89                 name_ = name
  90             if not spec:
  91                 continue
  92             if not spec.has_key(name):
  93                 continue
  94             idx_, mux_, bank_ = spec[name]
  95             idx_ = names[idx_]
  96             pin = {mux_: (name_, bank_)}
  97             if res.has_key(idx_):
  98                 res[idx_].update(pin)
  99             else:
 100                 res[idx_] = pin
 101
 102         self.pins = res
 103
 104
 105 def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 106     i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
 107     #for i in range(4):
 108     #    i2spins.append("DO%d+" % i)
 109     return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
 110                 origsuffix=suffix)
 111
 112 def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
 113     emmcpins = ['CMD+', 'CLK+']
 114     for i in range(8):
 115         emmcpins.append("D%d*" % i)
 116     return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
 117                 origsuffix=suffix)
 118
 119 def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
 120                 start=None, limit=None):
 121     sdmmcpins = ['CMD+', 'CLK+']
 122     for i in range(4):
 123         sdmmcpins.append("D%d*" % i)
 124     sdmmcpins = sdmmcpins[start:limit]
 125     return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
 126                 origsuffix=suffix)
 127
 128 def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
 129     spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
 130     return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
 131                 origsuffix=suffix)
 132
 133 def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 134     spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
 135     return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit,
 136                 origsuffix=suffix)
 137
 138 def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
 139     spipins = ['SDA*', 'SCL*']
 140     return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
 141                 origsuffix=suffix)
 142
 143 def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
 144     jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
 145     return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
 146                 origsuffix=suffix)
 147
 148 def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
 149     uartpins = ['TX+', 'RX-']
 150     return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
 151                 origsuffix=suffix)
 152
 153 def namesuffix(name, suffix, namelist):
 154     names = []
 155     for n in namelist:
 156         if n:
 157             names.append("%s%s_%s" % (name, suffix, n))
 158         else:
 159             names.append("%s_%s" % (name, suffix))
 160     return names
 161
 162 def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
 163     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 164     for i in range(8):
 165         ulpipins.append('D%d*' % i)
 166     return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
 167                 origsuffix=suffix)
 168
 169 def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
 170     uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
 171     return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
 172                 origsuffix=suffix)
 173
 174 def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
 175     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 176     for i in range(24):
 177         ttlpins.append("D%d+" % i)
 178     return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
 179                 origsuffix=suffix)
 180
 181 def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
 182     buspins = []
 183     for i in range(4):
 184         buspins.append("ERXD%d-" % i)
 185     for i in range(4):
 186         buspins.append("ETXD%d+" % i)
 187     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 188                 'EMDC+', 'EMDIO*',
 189                 'ETXEN+', 'ETXCK+', 'ECRS-',
 190                 'ECOL+', 'ETXERR+']
 191     return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
 192                 origsuffix=suffix)
 193
 194 def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 195     buspins = []
 196     for i in range(8):
 197         buspins.append("AD%d*" % i)
 198     for i in range(2):
 199         buspins.append("CS%d+" % i)
 200     buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
 201                 'A0', 'A1', 'TS', 'TBST',
 202                 'TSIZ0', 'TSIZ1']
 203     for i in range(4):
 204         buspins.append("BWE%d" % i)
 205     for i in range(2,6):
 206         buspins.append("CS%d+" % i)
 207     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 208                 origsuffix=suffix)
 209
 210 def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 211     buspins = []
 212     for i in range(8,32):
 213         buspins.append("AD%d*" % i)
 214     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 215                 origsuffix=suffix)
 216
 217 def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
 218     buspins = []
 219     for i in range(16):
 220         buspins.append("SDRDQM%d*" % i)
 221     for i in range(12):
 222         buspins.append("SDRAD%d+" % i)
 223     for i in range(8):
 224         buspins.append("SDRDQ%d+" % i)
 225     for i in range(3):
 226         buspins.append("SDRCS%d#+" % i)
 227     for i in range(2):
 228         buspins.append("SDRDQ%d+" % i)
 229     for i in range(2):
 230         buspins.append("SDRBA%d+" % i)
 231     buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
 232                 'SDRRST+']
 233     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
 234                 origsuffix=suffix)
 235
 236 def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 237     buspins = []
 238     for i in range(3,6):
 239         buspins.append("SDRCS%d#+" % i)
 240     for i in range(8,32):
 241         buspins.append("SDRDQ%d*" % i)
 242     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 243                 origsuffix=suffix)
 244
 245 def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
 246     buspins = []
 247     for i in range(8):
 248         buspins.append("MCUD%d*" % i)
 249     for i in range(8):
 250         buspins.append("MCUAD%d+" % (i+8))
 251     for i in range(6):
 252         buspins.append("MCUCS%d+" % i)
 253     for i in range(2):
 254         buspins.append("MCUNRB%d+" % i)
 255     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 256                 'MCURST+']
 257     return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
 258                 origsuffix=suffix)
 259
 260 def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
 261              spec=None):
 262     gpiopins = []
 263     for i in range(gpiooffs, gpiooffs+gpionum):
 264         gpiopins.append("%s%d*" % (bank, i))
 265     return Pins('GPIO', gpiopins, bankspec, suffix, offs, bank, mux, spec,
 266                 origsuffix=suffix)
 267
 268 def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 269     gpiopins = []
 270     for i in range(gpiooffs, gpiooffs+gpionum):
 271         gpiopins.append("%d*" % (i))
 272     return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
 273                 origsuffix=suffix)
 274
 275 def pwm(bankspec, suffix, offs, bank, mux=1, spec=None):
 276     return Pins('PWM', ['+', ], bankspec, suffix, offs, bank, mux, spec,
 277                 origsuffix=suffix)
 278
 279 def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 280     return _pinbank(bankspec, "GPIO", suffix, offs, bank, gpiooffs,
 281                               gpionum, mux=0, spec=None)
 282
 283 def pinmerge(pins, fn):
 284     # hack, store the function specs in the pins dict
 285     fname = fn.fname
 286     suffix = fn.origsuffix
 287     bank = fn.bank
 288
 289     if not hasattr(pins, 'fnspec'):
 290         pins.fnspec = pins
 291     if fname == 'GPIO':
 292         fname = fname + bank
 293     assert not pins.has_key('EINT')
 294     if not pins.fnspec.has_key(fname):
 295         pins.add_spec(fname, {})
 296     print "fname bank suffix", fname, bank, suffix
 297     if suffix or fname == 'EINT' or fname == 'PWM':
 298         specname = fname + suffix
 299     else:
 300         specname = fname + bank
 301     pins.fnspec[fname][specname] = fn
 302
 303
 304     # merge actual pins
 305     for (pinidx, v) in fn.pins.items():
 306         print "pinidx", pinidx
 307         pins.update(pinidx, v)
 308