src/spec/interfaces.py

   1 #!/usr/bin/env python
   2
   3 class Pinouts(object):
   4     def __init__(self):
   5         self.pins = {}
   6         self.fnspec = {}
   7
   8     def has_key(self, k):
   9         return self.pins.has_key(k)
  10
  11     def add_spec(self, k, v):
  12         self.fnspec[k] = v
  13
  14     def update(self, pinidx, v):
  15         if not self.pins.has_key(pinidx):
  16             self.pins[pinidx] = v
  17         else:
  18             self.pins[pinidx].update(v)
  19
  20     def keys(self):
  21         return self.pins.keys()
  22
  23     def items(self):
  24         return self.pins.items()
  25
  26     def get(self, k):
  27         return self.pins[k]
  28
  29     def __len__(self):
  30         return len(self.pins)
  31
  32     def __delitem__(self, k):
  33         del self.pins[k]
  34
  35     def __getitem__(self, k):
  36         return self.pins[k]
  37
  38
  39 class Pins(object):
  40
  41     def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
  42              spec=None, limit=None, origsuffix=None):
  43
  44         # function type can be in, out or inout, represented by - + *
  45         # strip function type out of each pin name
  46         self.fntype = {}
  47         for i in range(len(pingroup)):
  48             pname = pingroup[i]
  49             if not pname:
  50                 continue
  51             fntype = pname[-1]
  52             if fntype not in '+-*':
  53                 continue
  54             pname = pname[:-1]
  55             fntype = {'-': 'in', '+': 'out', '*': 'inout'}[fntype]
  56             self.fntype[pname] = fntype
  57             pingroup[i] = pname
  58
  59         self.fname = fname
  60         self.pingroup = pingroup
  61         self.bankspec = bankspec
  62         self.suffix = suffix
  63         self.origsuffix = origsuffix or suffix
  64         self.bank = bank
  65         self.mux = mux
  66
  67         # create consistent name suffixes
  68         pingroup = namesuffix(fname, suffix, pingroup)
  69         suffix = '' # hack
  70
  71         res = {}
  72         names = {}
  73         idx = 0
  74         for name in pingroup[:limit]:
  75             if suffix and name:
  76                 name_ = "%s_%s" % (name, suffix)
  77             else:
  78                 name_ = name
  79             if spec and spec.has_key(name):
  80                 continue
  81             pin = {mux: (name_, bank)}
  82             offs_bank, offs_ = offs
  83             idx_ = offs_ + idx
  84             idx += 1
  85             idx_ += bankspec[bank]
  86             res[idx_] = pin
  87             names[name] = idx_
  88         for name in pingroup:
  89             if suffix and name:
  90                 name_ = "%s_%s" % (name, suffix)
  91             else:
  92                 name_ = name
  93             if not spec:
  94                 continue
  95             if not spec.has_key(name):
  96                 continue
  97             idx_, mux_, bank_ = spec[name]
  98             idx_ = names[idx_]
  99             pin = {mux_: (name_, bank_)}
 100             if res.has_key(idx_):
 101                 res[idx_].update(pin)
 102             else:
 103                 res[idx_] = pin
 104
 105         self.pins = res
 106
 107
 108 def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 109     i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
 110     #for i in range(4):
 111     #    i2spins.append("DO%d+" % i)
 112     return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
 113                 origsuffix=suffix)
 114
 115 def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
 116     emmcpins = ['CMD+', 'CLK+']
 117     for i in range(8):
 118         emmcpins.append("D%d*" % i)
 119     return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
 120                 origsuffix=suffix)
 121
 122 def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
 123                 start=None, limit=None):
 124     sdmmcpins = ['CMD+', 'CLK+']
 125     for i in range(4):
 126         sdmmcpins.append("D%d*" % i)
 127     sdmmcpins = sdmmcpins[start:limit]
 128     return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
 129                 origsuffix=suffix)
 130
 131 def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
 132     spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
 133     return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
 134                 origsuffix=suffix)
 135
 136 def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 137     spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
 138     return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit,
 139                 origsuffix=suffix)
 140
 141 def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
 142     spipins = ['SDA*', 'SCL*']
 143     return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
 144                 origsuffix=suffix)
 145
 146 def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
 147     jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
 148     return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
 149                 origsuffix=suffix)
 150
 151 def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
 152     uartpins = ['TX+', 'RX-']
 153     return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
 154                 origsuffix=suffix)
 155
 156 def namesuffix(name, suffix, namelist):
 157     names = []
 158     for n in namelist:
 159         if n:
 160             names.append("%s%s_%s" % (name, suffix, n))
 161         else:
 162             names.append("%s_%s" % (name, suffix))
 163     return names
 164
 165 def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
 166     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 167     for i in range(8):
 168         ulpipins.append('D%d*' % i)
 169     return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
 170                 origsuffix=suffix)
 171
 172 def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
 173     uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
 174     return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
 175                 origsuffix=suffix)
 176
 177 def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
 178     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 179     for i in range(24):
 180         ttlpins.append("D%d+" % i)
 181     return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
 182                 origsuffix=suffix)
 183
 184 def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
 185     buspins = []
 186     for i in range(4):
 187         buspins.append("ERXD%d-" % i)
 188     for i in range(4):
 189         buspins.append("ETXD%d+" % i)
 190     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 191                 'EMDC+', 'EMDIO*',
 192                 'ETXEN+', 'ETXCK+', 'ECRS-',
 193                 'ECOL+', 'ETXERR+']
 194     return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
 195                 origsuffix=suffix)
 196
 197 def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 198     buspins = []
 199     for i in range(8):
 200         buspins.append("AD%d*" % i)
 201     for i in range(2):
 202         buspins.append("CS%d+" % i)
 203     buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
 204                 'A0', 'A1', 'TS', 'TBST',
 205                 'TSIZ0', 'TSIZ1']
 206     for i in range(4):
 207         buspins.append("BWE%d" % i)
 208     for i in range(2,6):
 209         buspins.append("CS%d+" % i)
 210     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 211                 origsuffix=suffix)
 212
 213 def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 214     buspins = []
 215     for i in range(8,32):
 216         buspins.append("AD%d*" % i)
 217     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 218                 origsuffix=suffix)
 219
 220 def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
 221     buspins = []
 222     for i in range(16):
 223         buspins.append("SDRDQM%d*" % i)
 224     for i in range(12):
 225         buspins.append("SDRAD%d+" % i)
 226     for i in range(8):
 227         buspins.append("SDRDQ%d+" % i)
 228     for i in range(3):
 229         buspins.append("SDRCS%d#+" % i)
 230     for i in range(2):
 231         buspins.append("SDRDQ%d+" % i)
 232     for i in range(2):
 233         buspins.append("SDRBA%d+" % i)
 234     buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
 235                 'SDRRST+']
 236     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
 237                 origsuffix=suffix)
 238
 239 def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 240     buspins = []
 241     for i in range(3,6):
 242         buspins.append("SDRCS%d#+" % i)
 243     for i in range(8,32):
 244         buspins.append("SDRDQ%d*" % i)
 245     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 246                 origsuffix=suffix)
 247
 248 def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
 249     buspins = []
 250     for i in range(8):
 251         buspins.append("MCUD%d*" % i)
 252     for i in range(8):
 253         buspins.append("MCUAD%d+" % (i+8))
 254     for i in range(6):
 255         buspins.append("MCUCS%d+" % i)
 256     for i in range(2):
 257         buspins.append("MCUNRB%d+" % i)
 258     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 259                 'MCURST+']
 260     return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
 261                 origsuffix=suffix)
 262
 263 def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
 264              spec=None):
 265     gpiopins = []
 266     for i in range(gpiooffs, gpiooffs+gpionum):
 267         gpiopins.append("%s%d*" % (bank, i))
 268     return Pins('GPIO', gpiopins, bankspec, suffix, offs, bank, mux, spec,
 269                 origsuffix=suffix)
 270
 271 def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 272     gpiopins = []
 273     for i in range(gpiooffs, gpiooffs+gpionum):
 274         gpiopins.append("%d*" % (i))
 275     return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
 276                 origsuffix=suffix)
 277
 278 def pwm(bankspec, suffix, offs, bank, mux=1, spec=None):
 279     return Pins('PWM', ['+', ], bankspec, suffix, offs, bank, mux, spec,
 280                 origsuffix=suffix)
 281
 282 def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 283     return _pinbank(bankspec, "GPIO", suffix, offs, bank, gpiooffs,
 284                               gpionum, mux=0, spec=None)
 285
 286 def pinmerge(pins, fn):
 287     # hack, store the function specs in the pins dict
 288     fname = fn.fname
 289     suffix = fn.origsuffix
 290     bank = fn.bank
 291
 292     if not hasattr(pins, 'fnspec'):
 293         pins.fnspec = pins
 294     if fname == 'GPIO':
 295         fname = fname + bank
 296     assert not pins.has_key('EINT')
 297     if not pins.fnspec.has_key(fname):
 298         pins.add_spec(fname, {})
 299     print "fname bank suffix", fname, bank, suffix
 300     if suffix or fname == 'EINT' or fname == 'PWM':
 301         specname = fname + suffix
 302     else:
 303         specname = fname + bank
 304     pins.fnspec[fname][specname] = fn
 305
 306
 307     # merge actual pins
 308     for (pinidx, v) in fn.pins.items():
 309         print "pinidx", pinidx
 310         pins.update(pinidx, v)
 311