src/spec/interfaces.py

   1 #!/usr/bin/env python
   2
   3 from copy import deepcopy
   4
   5
   6 def namesuffix(name, suffix, namelist):
   7     names = []
   8     for n in namelist:
   9         if n:
  10             names.append("%s%s_%s" % (name, suffix, n))
  11         else:
  12             names.append("%s_%s" % (name, suffix))
  13     return names
  14
  15
  16 class Pinouts(object):
  17     def __init__(self, bankspec):
  18         self.bankspec = bankspec
  19         self.pins = {}
  20         self.fnspec = {}
  21
  22     def __contains__(self, k):
  23         return k in self.pins
  24
  25     def has_key(self, k):
  26         return k in self.pins
  27
  28     def add_spec(self, k, v):
  29         self.fnspec[k] = v
  30
  31     def update(self, pinidx, v):
  32         if pinidx not in self.pins:
  33             self.pins[pinidx] = v
  34         else:
  35             self.pins[pinidx].update(v)
  36
  37     def keys(self):
  38         return self.pins.keys()
  39
  40     def items(self):
  41         return self.pins.items()
  42
  43     def get(self, k):
  44         return self.pins[k]
  45
  46     def __len__(self):
  47         return len(self.pins)
  48
  49     def __delitem__(self, k):
  50         del self.pins[k]
  51
  52     def __getitem__(self, k):
  53         return self.pins[k]
  54
  55     def i2s(self, suffix, offs, bank, mux=1, spec=None, limit=None):
  56         i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
  57         # for i in range(4):
  58         #    i2spins.append("DO%d+" % i)
  59         pins = Pins('IIS', i2spins, self.bankspec,
  60                     suffix, offs, bank, mux,
  61                     spec, limit, origsuffix=suffix)
  62         self.pinmerge(pins)
  63
  64     def emmc(self, suffix, offs, bank, mux=1, spec=None):
  65         emmcpins = ['CMD+', 'CLK+']
  66         for i in range(8):
  67             emmcpins.append("D%d*" % i)
  68         pins = Pins('MMC', emmcpins, self.bankspec,
  69                     suffix, offs, bank, mux,
  70                     spec, origsuffix=suffix)
  71         self.pinmerge(pins)
  72
  73     def sdmmc(self, suffix, offs, bank, mux=1, spec=None,
  74               start=None, limit=None):
  75         sdmmcpins = ['CMD+', 'CLK+']
  76         for i in range(4):
  77             sdmmcpins.append("D%d*" % i)
  78         sdmmcpins = sdmmcpins[start:limit]
  79         pins = Pins('SD', sdmmcpins, self.bankspec,
  80                     suffix, offs, bank, mux,
  81                     spec, origsuffix=suffix)
  82         self.pinmerge(pins)
  83
  84     def spi(self, suffix, offs, bank, mux=1, spec=None):
  85         spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
  86         pins = Pins('SPI', spipins, self.bankspec,
  87                     suffix, offs, bank, mux,
  88                     spec, origsuffix=suffix)
  89         self.pinmerge(pins)
  90
  91     def quadspi(self, suffix, offs, bank, mux=1, spec=None, limit=None):
  92         spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
  93         pins = Pins('QSPI', spipins, self.bankspec,
  94                     suffix, offs, bank, mux,
  95                     spec, limit, origsuffix=suffix)
  96         self.pinmerge(pins)
  97
  98     def i2c(self, suffix, offs, bank, mux=1, spec=None):
  99         spipins = ['SDA*', 'SCL*']
 100         pins = Pins('TWI', spipins, self.bankspec,
 101                     suffix, offs, bank, mux,
 102                     spec, origsuffix=suffix)
 103         self.pinmerge(pins)
 104
 105     def jtag(self, suffix, offs, bank, mux=1, spec=None):
 106         jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
 107         pins = Pins('JTAG', jtagpins, self.bankspec,
 108                     suffix, offs, bank, mux,
 109                     spec, origsuffix=suffix)
 110         self.pinmerge(pins)
 111
 112     def uart(self, suffix, offs, bank, mux=1, spec=None):
 113         uartpins = ['TX+', 'RX-']
 114         pins = Pins('UART', uartpins, self.bankspec,
 115                     suffix, offs, bank, mux,
 116                     spec, origsuffix=suffix)
 117         self.pinmerge(pins)
 118
 119     def ulpi(self, suffix, offs, bank, mux=1, spec=None):
 120         ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 121         for i in range(8):
 122             ulpipins.append('D%d*' % i)
 123         pins = Pins('ULPI', ulpipins, self.bankspec,
 124                     suffix, offs, bank, mux,
 125                     spec, origsuffix=suffix)
 126         self.pinmerge(pins)
 127
 128     def uartfull(self, suffix, offs, bank, mux=1, spec=None):
 129         uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
 130         pins = Pins('UARTQ', uartpins, self.bankspec,
 131                     suffix, offs, bank, mux,
 132                     spec, origsuffix=suffix)
 133         self.pinmerge(pins)
 134
 135     def rgbttl(self, suffix, offs, bank, mux=1, spec=None):
 136         ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 137         for i in range(24):
 138             ttlpins.append("D%d+" % i)
 139         pins = Pins('LCD', ttlpins, self.bankspec,
 140                     suffix, offs, bank, mux,
 141                     spec, origsuffix=suffix)
 142         self.pinmerge(pins)
 143
 144     def rgmii(self, suffix, offs, bank, mux=1, spec=None):
 145         buspins = []
 146         for i in range(4):
 147             buspins.append("ERXD%d-" % i)
 148         for i in range(4):
 149             buspins.append("ETXD%d+" % i)
 150         buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 151                     'EMDC+', 'EMDIO*',
 152                     'ETXEN+', 'ETXCK+', 'ECRS-',
 153                     'ECOL+', 'ETXERR+']
 154         pins = Pins('RG', buspins, self.bankspec,
 155                     suffix, offs, bank, mux,
 156                     spec, origsuffix=suffix)
 157         self.pinmerge(pins)
 158
 159     def flexbus1(self, suffix, offs, bank, mux=1, spec=None, limit=None):
 160         buspins = []
 161         for i in range(8):
 162             buspins.append("AD%d*" % i)
 163         for i in range(2):
 164             buspins.append("CS%d+" % i)
 165         buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
 166                     'A0', 'A1', 'TS', 'TBST',
 167                     'TSIZ0', 'TSIZ1']
 168         for i in range(4):
 169             buspins.append("BWE%d" % i)
 170         for i in range(2, 6):
 171             buspins.append("CS%d+" % i)
 172         pins = Pins('FB', buspins, self.bankspec,
 173                     suffix, offs, bank, mux,
 174                     spec, limit, origsuffix=suffix)
 175         self.pinmerge(pins)
 176
 177     def flexbus2(self, suffix, offs, bank, mux=1, spec=None, limit=None):
 178         buspins = []
 179         for i in range(8, 32):
 180             buspins.append("AD%d*" % i)
 181         pins = Pins('FB', buspins, self.bankspec,
 182                     suffix, offs, bank, mux,
 183                     spec, limit, origsuffix=suffix)
 184         self.pinmerge(pins)
 185
 186     def sdram1(self, suffix, offs, bank, mux=1, spec=None):
 187         buspins = []
 188         for i in range(16):
 189             buspins.append("SDRDQM%d*" % i)
 190         for i in range(12):
 191             buspins.append("SDRAD%d+" % i)
 192         for i in range(8):
 193             buspins.append("SDRDQ%d+" % i)
 194         for i in range(3):
 195             buspins.append("SDRCS%d#+" % i)
 196         for i in range(2):
 197             buspins.append("SDRDQ%d+" % i)
 198         for i in range(2):
 199             buspins.append("SDRBA%d+" % i)
 200         buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
 201                     'SDRRST+']
 202         pins = Pins('SDR', buspins, self.bankspec,
 203                     suffix, offs, bank, mux,
 204                     spec, origsuffix=suffix)
 205         self.pinmerge(pins)
 206
 207     def sdram2(self, suffix, offs, bank, mux=1, spec=None, limit=None):
 208         buspins = []
 209         for i in range(3, 6):
 210             buspins.append("SDRCS%d#+" % i)
 211         for i in range(8, 32):
 212             buspins.append("SDRDQ%d*" % i)
 213         pins = Pins('SDR', buspins, self.bankspec,
 214                     suffix, offs, bank, mux,
 215                     spec, limit, origsuffix=suffix)
 216         self.pinmerge(pins)
 217
 218     def mcu8080(self, suffix, offs, bank, mux=1, spec=None):
 219         buspins = []
 220         for i in range(8):
 221             buspins.append("MCUD%d*" % i)
 222         for i in range(8):
 223             buspins.append("MCUAD%d+" % (i + 8))
 224         for i in range(6):
 225             buspins.append("MCUCS%d+" % i)
 226         for i in range(2):
 227             buspins.append("MCUNRB%d+" % i)
 228         buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 229                     'MCURST+']
 230         pins = Pins('MCU', buspins, self.bankspec,
 231                     suffix, offs, bank, mux,
 232                     spec, origsuffix=suffix)
 233         self.pinmerge(pins)
 234
 235     def _pinbank(self, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
 236                  spec=None):
 237         gpiopins = []
 238         for i in range(gpiooffs, gpiooffs + gpionum):
 239             gpiopins.append("%s%d*" % (bank, i))
 240         pins = Pins(prefix, gpiopins, self.bankspec,
 241                     suffix, offs, bank, mux,
 242                     spec, origsuffix=suffix)
 243         self.pinmerge(pins)
 244
 245     def eint(self, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 246         gpiopins = []
 247         for i in range(gpiooffs, gpiooffs + gpionum):
 248             gpiopins.append("%d*" % (i))
 249         pins = Pins('EINT', gpiopins, self.bankspec,
 250                     suffix, offs, bank, mux,
 251                     spec, origsuffix=suffix)
 252         self.pinmerge(pins)
 253
 254     def pwm(self, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None):
 255         pwmpins = []
 256         for i in range(pwmoffs, pwmoffs + pwmnum):
 257             pwmpins.append("%d+" % (i))
 258         pins = Pins('PWM', pwmpins, self.bankspec,
 259                     suffix, offs, bank, mux,
 260                     spec, origsuffix=suffix)
 261         self.pinmerge(pins)
 262
 263     def gpio(self, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 264         self._pinbank("GPIO%s" % bank, suffix, offs, bank, gpiooffs,
 265                       gpionum, mux=0, spec=None)
 266
 267     def pinmerge(self, fn):
 268         # hack, store the function specs in the pins dict
 269         fname = fn.fname
 270         suffix = fn.origsuffix
 271         bank = fn.bank
 272
 273         if not hasattr(self, 'fnspec'):
 274             self.fnspec = pins
 275         if fname == 'GPIO':
 276             fname = fname + bank
 277         assert 'EINT' not in self
 278         if fname not in self.fnspec:
 279             self.add_spec(fname, {})
 280         if suffix or fname == 'EINT' or fname == 'PWM':
 281             specname = fname + suffix
 282         else:
 283             specname = fname
 284         print "fname bank specname suffix ", fname, bank, specname, repr(
 285             suffix)
 286         if specname in self.fnspec[fname]:
 287             # ok so some declarations may bring in different
 288             # names at different stages (EINT, PWM, flexbus1/2)
 289             # so we have to merge the names in.  main thing is
 290             # the pingroup
 291             tomerge = self.fnspec[fname][specname]
 292             for p in fn.pingroup:
 293                 if p not in tomerge.pingroup:
 294                     tomerge.pingroup.append(p)
 295             tomerge.pins.update(fn.pins)
 296             tomerge.fntype.update(fn.fntype)
 297         else:
 298             self.fnspec[fname][specname] = deepcopy(fn)
 299
 300         # merge actual pins
 301         for (pinidx, v) in fn.pins.items():
 302             self.update(pinidx, v)
 303
 304
 305 class Pins(object):
 306
 307     def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
 308                  spec=None, limit=None, origsuffix=None):
 309
 310         # function type can be in, out or inout, represented by - + *
 311         # strip function type out of each pin name
 312         self.fntype = {}
 313         for i in range(len(pingroup)):
 314             pname = pingroup[i]
 315             if not pname:
 316                 continue
 317             fntype = pname[-1]
 318             if fntype not in '+-*':
 319                 continue
 320             pname = pname[:-1]
 321             fntype = {'-': 'in', '+': 'out', '*': 'inout'}[fntype]
 322             self.fntype[pname] = fntype
 323             pingroup[i] = pname
 324
 325         self.fname = fname
 326         self.pingroup = pingroup
 327         self.bankspec = bankspec
 328         self.suffix = suffix
 329         self.origsuffix = origsuffix or suffix
 330         self.bank = bank
 331         self.mux = mux
 332
 333         # create consistent name suffixes
 334         pingroup = namesuffix(fname, suffix, pingroup)
 335         suffix = ''  # hack
 336
 337         res = {}
 338         names = {}
 339         idx = 0
 340         for name in pingroup[:limit]:
 341             if suffix and name:
 342                 name_ = "%s_%s" % (name, suffix)
 343             else:
 344                 name_ = name
 345             if spec and name in spec:
 346                 continue
 347             pin = {mux: (name_, bank)}
 348             offs_bank, offs_ = offs
 349             idx_ = offs_ + idx
 350             idx += 1
 351             idx_ += bankspec[bank]
 352             res[idx_] = pin
 353             names[name] = idx_
 354         for name in pingroup:
 355             if suffix and name:
 356                 name_ = "%s_%s" % (name, suffix)
 357             else:
 358                 name_ = name
 359             if not spec:
 360                 continue
 361             if name not in spec:
 362                 continue
 363             idx_, mux_, bank_ = spec[name]
 364             idx_ = names[idx_]
 365             pin = {mux_: (name_, bank_)}
 366             if idx_ in res:
 367                 res[idx_].update(pin)
 368             else:
 369                 res[idx_] = pin
 370
 371         self.pins = res