9 return self
.pins
.has_key(k
)
11 def add_spec(self
, k
, v
):
14 def update(self
, pinidx
, v
):
15 if not self
.pins
.has_key(pinidx
):
18 self
.pins
[pinidx
].update(v
)
21 return self
.pins
.keys()
24 return self
.pins
.items()
32 def __delitem__(self
, k
):
35 def __getitem__(self
, k
):
41 def __init__(self
, fname
, pingroup
, bankspec
, suffix
, offs
, bank
, mux
,
42 spec
=None, limit
=None, origsuffix
=None):
44 # function type can be in, out or inout, represented by - + *
45 # strip function type out of each pin name
47 for i
in range(len(pingroup
)):
52 if fntype
not in '+-*':
55 fntype
= {'-': 'in', '+': 'out', '*': 'inout'}[fntype
]
56 self
.fntype
[pname
] = fntype
60 self
.pingroup
= pingroup
61 self
.bankspec
= bankspec
63 self
.origsuffix
= origsuffix
or suffix
67 # create consistent name suffixes
68 pingroup
= namesuffix(fname
, suffix
, pingroup
)
74 for name
in pingroup
[:limit
]:
76 name_
= "%s_%s" % (name
, suffix
)
79 if spec
and spec
.has_key(name
):
81 pin
= {mux
: (name_
, bank
)}
82 offs_bank
, offs_
= offs
85 idx_
+= bankspec
[bank
]
90 name_
= "%s_%s" % (name
, suffix
)
95 if not spec
.has_key(name
):
97 idx_
, mux_
, bank_
= spec
[name
]
99 pin
= {mux_
: (name_
, bank_
)}
100 if res
.has_key(idx_
):
101 res
[idx_
].update(pin
)
108 def i2s(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
109 i2spins
= ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
111 # i2spins.append("DO%d+" % i)
112 return Pins('IIS', i2spins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
115 def emmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
116 emmcpins
= ['CMD+', 'CLK+']
118 emmcpins
.append("D%d*" % i
)
119 return Pins('MMC', emmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
122 def sdmmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None,
123 start
=None, limit
=None):
124 sdmmcpins
= ['CMD+', 'CLK+']
126 sdmmcpins
.append("D%d*" % i
)
127 sdmmcpins
= sdmmcpins
[start
:limit
]
128 return Pins('SD', sdmmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
131 def spi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
132 spipins
= ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
133 return Pins('SPI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
136 def quadspi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
137 spipins
= ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
138 return Pins('QSPI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
141 def i2c(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
142 spipins
= ['SDA*', 'SCL*']
143 return Pins('TWI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
146 def jtag(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
147 jtagpins
= ['MS+', 'DI-', 'DO+', 'CK+']
148 return Pins('JTAG', jtagpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
151 def uart(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
152 uartpins
= ['TX+', 'RX-']
153 return Pins('UART', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
156 def namesuffix(name
, suffix
, namelist
):
160 names
.append("%s%s_%s" % (name
, suffix
, n
))
162 names
.append("%s_%s" % (name
, suffix
))
165 def ulpi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
166 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
168 ulpipins
.append('D%d*' % i
)
169 return Pins('ULPI', ulpipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
172 def uartfull(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
173 uartpins
= ['TX+', 'RX-', 'CTS-', 'RTS+']
174 return Pins('UARTQ', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
177 def rgbttl(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
178 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
180 ttlpins
.append("D%d+" % i
)
181 return Pins('LCD', ttlpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
184 def rgmii(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
187 buspins
.append("ERXD%d-" % i
)
189 buspins
.append("ETXD%d+" % i
)
190 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
192 'ETXEN+', 'ETXCK+', 'ECRS-',
194 return Pins('RG', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
197 def flexbus1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
200 buspins
.append("AD%d*" % i
)
202 buspins
.append("CS%d+" % i
)
203 buspins
+= ['ALE', 'OE', 'RW', 'TA', 'CLK+',
204 'A0', 'A1', 'TS', 'TBST',
207 buspins
.append("BWE%d" % i
)
209 buspins
.append("CS%d+" % i
)
210 return Pins('FB', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
213 def flexbus2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
215 for i
in range(8,32):
216 buspins
.append("AD%d*" % i
)
217 return Pins('FB', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
220 def sdram1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
223 buspins
.append("SDRDQM%d*" % i
)
225 buspins
.append("SDRAD%d+" % i
)
227 buspins
.append("SDRDQ%d+" % i
)
229 buspins
.append("SDRCS%d#+" % i
)
231 buspins
.append("SDRDQ%d+" % i
)
233 buspins
.append("SDRBA%d+" % i
)
234 buspins
+= ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
236 return Pins('SDR', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
239 def sdram2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
242 buspins
.append("SDRCS%d#+" % i
)
243 for i
in range(8,32):
244 buspins
.append("SDRDQ%d*" % i
)
245 return Pins('SDR', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
248 def mcu8080(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
251 buspins
.append("MCUD%d*" % i
)
253 buspins
.append("MCUAD%d+" % (i
+8))
255 buspins
.append("MCUCS%d+" % i
)
257 buspins
.append("MCUNRB%d+" % i
)
258 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
260 return Pins('MCU', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
263 def _pinbank(bankspec
, prefix
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1,
266 for i
in range(gpiooffs
, gpiooffs
+gpionum
):
267 gpiopins
.append("%s%d*" % (bank
, i
))
268 return Pins('GPIO', gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
271 def eint(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
273 for i
in range(gpiooffs
, gpiooffs
+gpionum
):
274 gpiopins
.append("%d*" % (i
))
275 return Pins('EINT', gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
278 def pwm(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
279 return Pins('PWM', ['+', ], bankspec
, suffix
, offs
, bank
, mux
, spec
,
282 def gpio(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
283 return _pinbank(bankspec
, "GPIO", suffix
, offs
, bank
, gpiooffs
,
284 gpionum
, mux
=0, spec
=None)
286 def pinmerge(pins
, fn
):
287 # hack, store the function specs in the pins dict
289 suffix
= fn
.origsuffix
292 if not hasattr(pins
, 'fnspec'):
296 assert not pins
.has_key('EINT')
297 if not pins
.fnspec
.has_key(fname
):
298 pins
.add_spec(fname
, {})
299 print "fname bank suffix", fname
, bank
, suffix
300 if suffix
or fname
== 'EINT' or fname
== 'PWM':
301 specname
= fname
+ suffix
303 specname
= fname
+ bank
304 pins
.fnspec
[fname
][specname
] = fn
308 for (pinidx
, v
) in fn
.pins
.items():
309 print "pinidx", pinidx
310 pins
.update(pinidx
, v
)