3 from copy
import deepcopy
11 return self
.pins
.has_key(k
)
13 def add_spec(self
, k
, v
):
16 def update(self
, pinidx
, v
):
17 if not self
.pins
.has_key(pinidx
):
20 self
.pins
[pinidx
].update(v
)
23 return self
.pins
.keys()
26 return self
.pins
.items()
34 def __delitem__(self
, k
):
40 def __init__(self
, fname
, pingroup
, bankspec
, suffix
, offs
, bank
, mux
,
41 spec
=None, limit
=None, origsuffix
=None):
43 self
.pingroup
= pingroup
44 self
.bankspec
= bankspec
46 self
.origsuffix
= origsuffix
or suffix
50 pingroup
= namesuffix(fname
, suffix
, pingroup
)
56 for name
in pingroup
[:limit
]:
58 name_
= "%s_%s" % (name
, suffix
)
61 if spec
and spec
.has_key(name
):
63 pin
= {mux
: (name_
, bank
)}
64 offs_bank
, offs_
= offs
67 idx_
+= bankspec
[bank
]
72 name_
= "%s_%s" % (name
, suffix
)
77 if not spec
.has_key(name
):
79 idx_
, mux_
, bank_
= spec
[name
]
81 pin
= {mux_
: (name_
, bank_
)}
90 def i2s(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
91 i2spins
= ['MCK', 'BCK', 'LRCK', 'DI']
93 i2spins
.append("DO%d" % i
)
94 return Pins('IIS', i2spins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
97 def emmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
98 emmcpins
= ['CMD', 'CLK']
100 emmcpins
.append("D%d" % i
)
101 return Pins('MMC', emmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
104 def sdmmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None,
105 start
=None, limit
=None):
106 sdmmcpins
= ['CMD', 'CLK']
108 sdmmcpins
.append("D%d" % i
)
109 sdmmcpins
= sdmmcpins
[start
:limit
]
110 return Pins('SD', sdmmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
113 def spi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
114 spipins
= ['CLK', 'NSS', 'MOSI', 'MISO', 'NSS']
115 return Pins('SPI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
118 def quadspi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
119 spipins
= ['CK', 'NSS', 'IO0', 'IO1', 'IO2', 'IO3']
120 return Pins('QSPI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
123 def i2c(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
124 spipins
= ['SDA', 'SCL']
125 return Pins('TWI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
128 def jtag(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
129 uartpins
= ['MS', 'DI', 'DO', 'CK']
130 return Pins('JTAG', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
133 def uart(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
134 uartpins
= ['TX', 'RX']
135 return Pins('UART', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
138 def namesuffix(name
, suffix
, namelist
):
142 names
.append("%s%s_%s" % (name
, suffix
, n
))
144 names
.append("%s_%s" % (name
, suffix
))
147 def ulpi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
148 ulpipins
= ['CK', 'DIR', 'STP', 'NXT']
150 ulpipins
.append('D%d' % i
)
151 return Pins('ULPI', ulpipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
154 def uartfull(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
155 uartpins
= ['TX', 'RX', 'CTS', 'RTS']
156 return Pins('UARTQ', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
159 def rgbttl(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
160 ttlpins
= ['CK', 'DE', 'HS', 'VS']
162 ttlpins
.append("D%d" % i
)
163 return Pins('LCD', ttlpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
166 def rgmii(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
169 buspins
.append("ERXD%d" % i
)
171 buspins
.append("ETXD%d" % i
)
172 buspins
+= ['ERXCK', 'ERXERR', 'ERXDV',
174 'ETXEN', 'ETXCK', 'ECRS',
176 return Pins('RG', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
179 def flexbus1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
182 buspins
.append("AD%d" % i
)
184 buspins
.append("CS%d" % i
)
185 buspins
+= ['ALE', 'OE', 'RW', 'TA', 'CLK',
186 'A0', 'A1', 'TS', 'TBST',
189 buspins
.append("BWE%d" % i
)
191 buspins
.append("CS%d" % i
)
192 return Pins('FB', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
195 def flexbus2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
197 for i
in range(8,32):
198 buspins
.append("AD%d" % i
)
199 return Pins('FB', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
202 def sdram1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
205 buspins
.append("SDRDQM%d" % i
)
207 buspins
.append("SDRAD%d" % i
)
209 buspins
.append("SDRDQ%d" % i
)
211 buspins
.append("SDRCS%d#" % i
)
213 buspins
.append("SDRDQ%d" % i
)
215 buspins
.append("SDRBA%d" % i
)
216 buspins
+= ['SDRCKE', 'SDRRAS#', 'SDRCAS#', 'SDRWE#',
218 return Pins('SDR', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
221 def sdram2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
224 buspins
.append("SDRCS%d#" % i
)
225 for i
in range(8,32):
226 buspins
.append("SDRDQ%d" % i
)
227 return Pins('SDR', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
230 def mcu8080(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
233 buspins
.append("MCUD%d" % i
)
235 buspins
.append("MCUAD%d" % (i
+8))
237 buspins
.append("MCUCS%d" % i
)
239 buspins
.append("MCUNRB%d" % i
)
240 buspins
+= ['MCUCD', 'MCURD', 'MCUWR', 'MCUCLE', 'MCUALE',
242 return Pins('MCU', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
245 def _pinbank(bankspec
, prefix
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1,
248 for i
in range(gpiooffs
, gpiooffs
+gpionum
):
249 gpiopins
.append("%s%d" % (bank
, i
))
250 return Pins('GPIO', gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
253 def eint(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
255 for i
in range(gpiooffs
, gpiooffs
+gpionum
):
256 gpiopins
.append("%d" % (i
))
257 return Pins('EINT', gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
260 def pwm(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
261 return Pins('PWM', ['', ], bankspec
, suffix
, offs
, bank
, mux
, spec
,
264 def gpio(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
265 return _pinbank(bankspec
, "GPIO", suffix
, offs
, bank
, gpiooffs
,
266 gpionum
, mux
=0, spec
=None)
269 print "| Pin | Mux0 | Mux1 | Mux2 | Mux3 |"
270 print "| --- | ----------- | ----------- | ----------- | ----------- |"
274 pdata
= pins
.get(pin
)
275 res
= '| %3d |' % pin
277 if not pdata
.has_key(mux
):
280 name
, bank
= pdata
[mux
]
281 res
+= " %s %-9s |" % (bank
, name
)
287 if not f
.startswith('FB_'):
291 return f2
[0], int(f2
[1])
294 while f
and not f
[0].isdigit():
297 return a
, int(f
) if f
else None
307 def find_fn(fname
, names
):
309 if fname
.startswith(n
):
312 def display_fns(bankspec
, pins
, function_names
):
313 fn_names
= function_names
.keys()
315 for (pin
, pdata
) in pins
.items():
316 for mux
in range(1,4): # skip GPIO for now
317 if not pdata
.has_key(mux
):
319 name
, bank
= pdata
[mux
]
320 assert name
!= None, str(bank
)
321 if not fns
.has_key(name
):
323 fns
[name
].append((pin
-bankspec
[bank
], mux
, bank
))
329 fnbase
= find_fn(fname
, fn_names
)
330 #print "name", fname, fnbase
331 if fnbase
!= current_fn
:
332 if current_fn
is not None:
334 print "## %s" % fnbase
336 print function_names
[fnbase
]
339 print "* %-9s :" % fname
,
340 for (pin
, mux
, bank
) in fns
[fname
]:
341 print "%s%d/%d" % (bank
, pin
, mux
),
346 def check_functions(title
, bankspec
, fns
, pins
, required
, eint
, pwm
,
349 pins
= deepcopy(pins
)
350 if descriptions
is None:
353 print "# Pinmap for %s" % title
357 for name
in required
:
360 if descriptions
and descriptions
.has_key(name
):
361 print descriptions
[name
]
364 name
= name
.split(':')
366 findbank
= name
[0][0]
367 findmux
= int(name
[0][1:])
373 name
= name
.split('/')
384 if not fname
.startswith(name
):
386 for pin
, mux
, bank
in fns
[fname
]:
387 if findbank
is not None:
392 pin_
= pin
+ bankspec
[bank
]
393 if pins
.has_key(pin_
):
394 pinfound
[pin_
] = (fname
, pin_
, bank
, pin
, mux
)
396 pinidx
= pinfound
.keys()
400 fname
, pin_
, bank
, pin
, mux
= pinfound
[pin_
]
404 if len(found
) > count
:
407 print "* %s %d %s%d/%d" % (fname
, pin_
, bank
, pin
, mux
)
413 for name
in descriptions
.keys():
414 if not name
.startswith('GPIO'):
429 if descriptions
and descriptions
.has_key(fname
):
430 desc
= ': %s' % descriptions
[fname
]
433 pin_
= pin
+ bankspec
[bank
]
434 if not pins
.has_key(pin_
):
438 print "* %-8s %d %s%-2d %s" % (fname
, pin_
, bank
, pin
, desc
)
442 display_group(bankspec
, "EINT", eint
, fns
, pins
, descriptions
)
444 display_group(bankspec
, "PWM", pwm
, fns
, pins
, descriptions
)
446 print "## Unused Pinouts (spare as GPIO) for '%s'" % title
448 if descriptions
and descriptions
.has_key('GPIO'):
449 print descriptions
['GPIO']
456 def display_group(bankspec
, title
, todisplay
, fns
, pins
, descriptions
):
457 print "## %s" % title
461 for fname
in todisplay
:
463 if descriptions
and descriptions
.has_key(fname
):
464 desc
= ': %s' % descriptions
[fname
]
465 fname
= fname
.split(':')
467 findbank
= fname
[0][0]
468 findmux
= int(fname
[0][1:])
474 for (pin
, mux
, bank
) in fns
[fname
]:
475 if findbank
is not None:
482 pin_
= pin
+ bankspec
[bank
]
483 if not pins
.has_key(pin_
):
487 print "* %s %d %s%d/%d %s" % (fname
, pin_
, bank
, pin
, mux
, desc
)
490 def pinmerge(pins
, fn
):
491 # hack, store the function specs in the pins dict
493 suffix
= fn
.origsuffix
496 if not hasattr(pins
, 'fnspec'):
500 assert not pins
.has_key('EINT')
501 if not pins
.fnspec
.has_key(fname
):
502 pins
.add_spec(fname
, {})
503 print "fname bank suffix", fname
, bank
, suffix
504 if suffix
or fname
== 'EINT' or fname
== 'PWM':
505 specname
= fname
+ suffix
507 specname
= fname
+ bank
508 pins
.fnspec
[fname
][specname
] = fn
512 for (pinidx
, v
) in fn
.pins
.items():
513 print "pinidx", pinidx
514 pins
.update(pinidx
, v
)
516 def display_fixed(fixed
, offs
):
521 for pin
, k
in enumerate(fkeys
):
526 for name
in fixed
[k
]:
530 if prevname
[:2] == name
[:2] and linecount
!= 0:
536 print "* %d: %d %s" % (pin_
, pin
, name
),