2 # see https://bugs.libre-soc.org/show_bug.cgi?id=304
4 from spec
.base
import PinSpec
5 from parse
import Parse
8 from pprint
import pprint
9 from spec
.ifaceprint
import display
, display_fns
, check_functions
10 from spec
.ifaceprint
import display_fixed
11 from collections
import OrderedDict
14 pinbanks
= OrderedDict((
42 'PWM': 'PWM (pulse-width modulation)',
43 'MSPI0': 'SPI Master 1 (general)',
44 'MSPI1': 'SPI Master 2 (SDCard)',
45 'UART0': 'UART (TX/RX) 1',
46 'SYS': 'System Control',
48 'EINT': 'External Interrupt',
51 'TWI': 'I2C Master 1',
56 #'LPC1': 'Low Pincount Interface 1',
57 #'LPC2': 'Low Pincount Interface 2',
60 ps
= PinSpec(pinbanks
, fixedpins
, function_names
)
62 ps
.vss("", ('N', 0), 0, 0, 1)
63 ps
.vdd("", ('N', 1), 0, 0, 1)
64 ps
.sdram1("", ('N', 2), 0, 0, 30)
65 ps
.vss("", ('N', 30), 0, 1, 1)
66 ps
.vdd("", ('N', 31), 0, 1, 1)
68 ps
.vss("", ('E', 0), 0, 2, 1)
69 ps
.sdram2("", ('E', 1), 0, 0, 12)
70 ps
.vdd("", ('E', 13), 0, 2, 1)
71 ps
.gpio("", ('E', 14), 0, 8, 8)
72 ps
.vss("", ('E', 23), 0, 3, 1)
73 ps
.jtag("", ('E', 24), 0, 0, 4)
74 ps
.vdd("", ('E', 31), 0, 3, 1)
76 ps
.vss("", ('S', 0), 0, 4, 1)
77 ps
.sys("", ('S', 1), 0, 0, 7)
78 ps
.vdd("", ('S', 8), 0, 4, 1)
79 ps
.i2c("", ('S', 9), 0, 0, 2)
80 ps
.mspi("0", ('S', 15), 0)
81 ps
.uart("0", ('S', 20), 0)
82 ps
.vss("", ('S', 22), 0, 5, 1)
83 ps
.gpio("", ('S', 23), 0, 0, 8)
84 ps
.vdd("", ('S', 31), 0, 5, 1)
86 ps
.vss("", ('W', 0), 0, 6, 1)
87 ps
.pwm("", ('W', 1), 0, 0, 2)
88 ps
.eint("", ('W', 3), 0, 0, 3)
89 ps
.mspi("1", ('W', 6), 0)
90 ps
.vdd("", ('W', 10), 0, 6, 1)
91 ps
.sdmmc("0", ('W', 11), 0)
92 ps
.vss("", ('W', 17), 0, 7, 1)
93 ps
.vdd("", ('W', 31), 0, 7, 1)
94 #ps.mspi("0", ('W', 8), 0)
95 #ps.mspi("1", ('W', 8), 0)
97 #ps.mquadspi("1", ('S', 0), 0)
99 print "ps clocks", ps
.clocks
101 # Scenarios below can be spec'd out as either "find first interface"
102 # by name/number e.g. SPI1, or as "find in bank/mux" which must be
103 # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
104 # EINT and PWM are grouped together, specially, but may still be spec'd
105 # using "BM:Name". Pins are removed in-order as listed from
106 # lists (interfaces, EINTs, PWMs) from available pins.
108 ls180
= ['SD0', 'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
110 'TWI', 'MSPI0', 'MSPI1', 'SDR']
112 ls180_pwm
= []#['B0:PWM_0']
114 'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
115 'and UART2, for debug purposes',
124 'B1:LCD/22': '18-bit RGB/TTL LCD',
125 'ULPI0/8': 'user-facing: internal (on Card), USB-OTG ULPI PHY',
126 'ULPI1': 'dual USB2 Host ULPI PHY'
129 ps
.add_scenario("Libre-SOC 180nm", ls180
, ls180_eint
, ls180_pwm
,
135 # map pins to litex name conventions, primarily for use in coriolis2
136 def pinparse(psp
, pinspec
):
137 p
= Parse(pinspec
, verify
=False)
140 print p
.muxed_cells_bank
146 pads
= {'N': pn
, 'S': ps
, 'E': pe
, 'W': pw
}
152 for (padnum
, name
, _
), bank
in zip(p
.muxed_cells
, p
.muxed_cells_bank
):
154 domain
= None # TODO, get this from the PinSpec. sigh
156 start
= p
.bankstart
[bank
]
157 banknum
= padnum
- start
158 print banknum
, name
, bank
161 if name
.startswith('vss'):
162 #name = 'p_vssick_' + name[-1]
167 elif name
.startswith('vdd'):
168 #name = 'p_vddick_' + name[-1]
173 elif name
.startswith('sys'):
175 if name
== 'sys_clk':
177 elif name
== 'sys_rst':
178 #name = 'p_sys_rst_1'
179 iopads
.append([name
, name
, name
])
180 padbank
[banknum
] = name
181 print "sys_rst add", bank
, banknum
, name
183 elif name
== 'sys_pllclk':
185 elif name
== 'sys_pllout':
186 name
= 'sys_pll_48_o'
187 iopads
.append(['p_' + name
, name
, name
])
188 elif name
.startswith('sys_csel'):
190 name2
= 'sys_clksel_i(%s)' % i
191 name
= 'p_sys_clksel_' + i
192 iopads
.append([name
, name2
, name2
])
194 # iopads.append([pname, name, name])
195 print "sys pad", name
197 elif name
.startswith('mspi0') or name
.startswith('mspi1'):
202 elif suffix
== 'nss':
204 if name
.startswith('mspi1'):
205 prefix
= 'spi_master_'
207 prefix
= 'spisdcard_'
208 name
= prefix
+ suffix
209 iopads
.append(['p_' + name
, name
, name
])
211 elif name
.startswith('sd0'):
213 if name
.startswith('sd0_d'):
215 name
= 'sdcard_data' + i
216 name2
= 'sdcard_data_%%s(%s)' % i
217 pad
= ['p_' + name
, name
, name2
% 'o', name2
% 'i',
220 elif name
.startswith('sd0_cmd'):
222 name2
= 'sdcard_cmd_%s'
223 pad
= ['p_' + name
, name
, name2
% 'o', name2
% 'i', name2
% 'oe']
226 name
= 'sdcard_' + name
[4:]
227 iopads
.append(['p_' + name
, name
, name
])
229 elif name
.startswith('sdr'):
231 if name
== 'sdr_clk':
233 iopads
.append(['p_' + name
, name
, name
])
234 elif name
.startswith('sdr_ad'):
236 name
= 'sdram_a_' + i
237 name2
= 'sdram_a(%s)' % i
238 iopads
.append(['p_' + name
, name2
, name2
])
239 elif name
.startswith('sdr_ba'):
241 name
= 'sdram_ba_' + i
242 name2
= 'sdram_ba(%s)' % i
243 iopads
.append(['p_' + name
, name2
, name2
])
244 elif name
.startswith('sdr_dqm'):
246 name
= 'sdram_dm_' + i
247 name2
= 'sdram_dm(%s)' % i
248 iopads
.append(['p_' + name
, name2
, name2
])
249 elif name
.startswith('sdr_d'):
251 name
= 'sdram_dq_' + i
252 name2
= 'sdram_dq_%%s(%s)' % i
253 pad
= ['p_' + name
, name
, name2
% 'o', name2
% 'i', 'sdram_dq_oe']
255 elif name
== 'sdr_csn0':
257 iopads
.append(['p_' + name
, name
, name
])
258 elif name
[-1] == 'n':
259 name
= 'sdram_' + name
[4:-1] + '_n'
260 iopads
.append(['p_' + name
, name
, name
])
262 name
= 'sdram_' + name
[4:]
263 iopads
.append(['p_' + name
, name
, name
])
265 elif name
.startswith('uart'):
267 name
= 'uart_' + name
[6:]
268 iopads
.append(['p_' + name
, name
, name
])
270 elif name
.startswith('gpio'):
274 name2
= 'gpio_%%s(%s)' % i
275 pad
= ['p_' + name
, name
, name2
% 'o', name2
% 'i', name2
% 'oe']
276 print ("GPIO pad", name
, pad
)
279 elif name
.startswith('twi'):
281 name
= 'i2c' + name
[3:]
282 if name
.startswith('i2c_sda'):
284 pad
= ['p_' + name
, name
, name2
% 'o', name2
% 'i', name2
% 'oe']
285 print ("I2C pad", name
, pad
)
288 iopads
.append(['p_' + name
, name
, name
])
290 elif name
.startswith('eint'):
293 name2
= 'eint(%s)' % i
294 pad
= ['p_' + name
, name2
, name2
]
297 elif name
.startswith('pwm'):
299 pad
= ['p_' + name
, name
, name
]
302 pad
= ['p_' + name
, name
, name
]
304 print ("GPIO pad", name
, pad
)
307 if name
and name
.startswith('jtag'):
310 if name
and not name
.startswith('p_'):
313 padbank
[banknum
] = name
315 if domain
is not None:
316 if domain
not in domains
:
318 domains
[domain
].append(name
)
320 if domain
in psp
.clocks
and orig_name
.startswith(dl
):
321 clk
= psp
.clocks
[domain
]
322 if clk
.lower() in orig_name
: # TODO, might over-match
323 clocks
[domain
] = name
326 pe
[13] = 'p_vddeck_0'
327 pe
[23] = 'p_vsseck_0'
328 pw
[10] = 'p_vddick_0'
329 pw
[17] = 'p_vssick_0'
333 for pl
in [pe
, pw
, pn
, ps
]:
334 for i
in range(len(pl
)):
336 pl
[i
] = 'nc_%d' % nc_idx
352 print "chip domains (excluding sys-default)"
354 print "chip clocks (excluding sys-default)"
362 'pads.instances' : iopads
,
363 'chip.domains' : domains
,
364 'chip.clocks' : clocks
,
367 chip
= json
.dumps(chip
)
368 with
open("ls180/litex_pinpads.json", "w") as f
: