2 # see https://bugs.libre-soc.org/show_bug.cgi?id=304
4 from spec
.base
import PinSpec
6 from spec
.ifaceprint
import display
, display_fns
, check_functions
7 from spec
.ifaceprint
import display_fixed
8 from collections
import OrderedDict
11 pinbanks
= OrderedDict((
39 'PWM': 'PWM (pulse-width modulation)',
40 'MSPI0': 'SPI (Serial Peripheral Interface) Master 1',
41 'MSPI1': 'SPI (Serial Peripheral Interface) Master 2',
42 'UART0': 'UART (TX/RX) 1',
43 'CLK': 'System Clock',
46 'EINT': 'External Interrupt',
53 #'LPC1': 'Low Pincount Interface 1',
54 #'LPC2': 'Low Pincount Interface 2',
57 ps
= PinSpec(pinbanks
, fixedpins
, function_names
)
59 ps
.vss("", ('N', 0), 0, 0, 1)
60 ps
.vdd("", ('N', 1), 0, 0, 1)
61 ps
.sdram1("", ('N', 2), 0, 0, 30)
62 ps
.vss("", ('N', 30), 0, 1, 1)
63 ps
.vdd("", ('N', 31), 0, 1, 1)
65 ps
.vss("", ('E', 0), 0, 2, 1)
66 ps
.sdram2("", ('E', 1), 0, 0, 12)
67 ps
.vdd("", ('E', 13), 0, 2, 1)
68 ps
.gpio("", ('E', 14), 0, 8, 8)
69 ps
.vss("", ('E', 23), 0, 3, 1)
70 ps
.jtag("", ('E', 24), 0, 0, 4)
71 ps
.vdd("", ('E', 31), 0, 3, 1)
73 ps
.vss("", ('S', 0), 0, 4, 1)
74 ps
.clk("", ('S', 1), 0, 0, 1)
75 ps
.rst("", ('S', 2), 0, 0, 1)
76 ps
.mspi("0", ('S', 4), 0)
77 ps
.uart("0", ('S', 8), 0)
78 ps
.gpio("", ('S', 14), 0, 0, 8)
79 ps
.vdd("", ('S', 31), 0, 4, 1)
81 ps
.vss("", ('W', 0), 0, 5, 1)
82 ps
.pwm("", ('W', 1), 0, 0, 2)
83 ps
.eint("", ('W', 3), 0, 0, 3)
84 ps
.mspi("1", ('W', 6), 0)
85 ps
.vdd("", ('W', 10), 0, 5, 1)
86 ps
.sdmmc("0", ('W', 11), 0)
87 ps
.vss("", ('W', 17), 0, 6, 1)
88 ps
.vdd("", ('W', 31), 0, 6, 1)
89 #ps.mspi("0", ('W', 8), 0)
90 #ps.mspi("1", ('W', 8), 0)
92 #ps.mquadspi("1", ('S', 0), 0)
94 # Scenarios below can be spec'd out as either "find first interface"
95 # by name/number e.g. SPI1, or as "find in bank/mux" which must be
96 # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
97 # EINT and PWM are grouped together, specially, but may still be spec'd
98 # using "BM:Name". Pins are removed in-order as listed from
99 # lists (interfaces, EINTs, PWMs) from available pins.
101 ls180
= ['SD0', 'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
102 'VDD', 'VSS', 'CLK', 'RST',
103 'TWI0', 'MSPI0', 'MSPI1', 'SDR']
105 ls180_pwm
= []#['B0:PWM_0']
107 'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
108 'and UART2, for debug purposes',
118 'B1:LCD/22': '18-bit RGB/TTL LCD',
119 'ULPI0/8': 'user-facing: internal (on Card), USB-OTG ULPI PHY',
120 'ULPI1': 'dual USB2 Host ULPI PHY'
123 ps
.add_scenario("Libre-SOC 180nm", ls180
, ls180_eint
, ls180_pwm
,