src/spec/ls2.py

   1 #!/usr/bin/env python
   2 # see https://bugs.libre-soc.org/show_bug.cgi?id=739
   3
   4 from spec.base import PinSpec
   5 from parse import Parse
   6
   7 from pprint import pprint
   8 from spec.ifaceprint import display, display_fns, check_functions
   9 from spec.ifaceprint import display_fixed
  10 from collections import OrderedDict
  11
  12 def pinspec():
  13     pinbanks = OrderedDict((
  14         ('N', (32, 4)),
  15         ('E', (32, 4)),
  16         ('S', (32, 4)),
  17         ('W', (32, 4)),
  18     ))
  19     fixedpins = {
  20         'CTRL_SYS': [
  21             'TEST',
  22             'JTAG_SEL',
  23             'UBOOT_SEL',
  24             'NMI#',
  25             'RESET#',
  26             'CLK24M_IN',
  27             'CLK24M_OUT',
  28             'PLLTEST',
  29             'PLLREGIO',
  30             'PLLVP25',
  31             'PLLDV',
  32             'PLLVREG',
  33             'PLLGND',
  34         ],
  35         'POWER_GPIO': [
  36             'VDD_GPIOB',
  37             'GND_GPIOB',
  38         ]}
  39     fixedpins = {}
  40     function_names = {
  41                       'RG0': 'Gigabit Ethernet 0',
  42                       'PWM': 'PWM (pulse-width modulation)',
  43                       'MSPI0': 'SPI Master 1 (general)',
  44                       'MSPI1': 'SPI Master 2 (SDCard)',
  45                       'UART0': 'UART (TX/RX) 1',
  46                       'SYS': 'System Control',
  47                       'GPIO': 'GPIO',
  48                       'EINT': 'External Interrupt',
  49                       'PWM': 'PWM',
  50                       'JTAG': 'JTAG',
  51                       'MTWI': 'I2C Master 1',
  52                       'SD0': 'SD/MMC 1',
  53                       'SDR': 'SDRAM',
  54                       'VDD': 'Power',
  55                       'VSS': 'GND',
  56                       #'LPC1': 'Low Pincount Interface 1',
  57                       #'LPC2': 'Low Pincount Interface 2',
  58                       }
  59
  60     ps = PinSpec(pinbanks, fixedpins, function_names)
  61
  62     ps.sdram1("", ('W', 0), 0, 15, 6, rev=True) # AD4-9, turned round
  63     ps.vdd("E", ('W', 6), 0, 0, 1)
  64     ps.vss("E", ('W', 7), 0, 0, 1)
  65     ps.vdd("I", ('W', 8), 0, 0, 1)
  66     ps.vss("I", ('W', 9), 0, 0, 1)
  67     ps.sdram1("", ('W', 10), 0, 0, 15, rev=True) # SDRAM DAM0, D0-7, AD0-3
  68     ps.mi2c("", ('W', 26), 0, 0, 2)
  69     ps.vss("I", ('W', 28), 0, 1, 1)
  70     ps.vdd("I", ('W', 29), 0, 1, 1)
  71     ps.vss("E", ('W', 30), 0, 1, 1)
  72     ps.vdd("E", ('W', 31), 0, 1, 1)
  73
  74     ps.gpio("", ('S', 0), 0, 0, 4) # GPIO 0-4
  75     ps.sdram2("", ('S', 0), 1, 0, 4) # 1st 4, AD10-12,DQM1
  76     ps.vdd("E", ('S', 4), 0, 2, 1)
  77     ps.vss("E", ('S', 5), 0, 2, 1)
  78     ps.vdd("I", ('S', 6), 0, 2, 1)
  79     ps.vss("I", ('S', 7), 0, 2, 1)
  80     ps.gpio("", ('S', 8), 0, 4, 14) # GPIO 5-17
  81     ps.sdram2("", ('S', 8), 1, 4, 8) # D8-15
  82     ps.sdram1("", ('S', 16), 1, 21, 9) # clk etc.
  83     ps.vss("I", ('S', 22), 0, 3, 1)
  84     ps.vdd("I", ('S', 23), 0, 3, 1)
  85     ps.vss("E", ('S', 24), 0, 3, 1)
  86     ps.vdd("E", ('S', 25), 0, 3, 1)
  87     ps.gpio("", ('S', 26), 0, 18, 6) # GPIO 18-23
  88     ps.uart("0", ('S', 26), 1)
  89     ps.mspi("0", ('S', 28), 1)
  90
  91     ps.gpio("", ('E', 0), 0, 0, 4) # GPIO 0-3
  92     ps.rgmii("1", ('E', 0), 1, 0, 4) # RXD0-3
  93     ps.vss("E", ('E', 4), 0, 4, 1)
  94     ps.vdd("E", ('E', 5), 0, 4, 1)
  95     ps.vdd("I", ('E', 6), 0, 4, 1)
  96     ps.vss("I", ('E', 7), 0, 4, 1)
  97     ps.gpio("", ('E', 8), 0, 6, 10) # GPIO 4-13
  98     ps.rgmii("1", ('E', 8), 1, 4, 10) # more RGMII-2
  99     ps.jtag("", ('E', 18), 0, 0, 4)
 100     ps.vss("I", ('E', 22), 0, 5, 1)
 101     ps.vdd("I", ('E', 23), 0, 5, 1)
 102     ps.vss("E", ('E', 24), 0, 5, 1)
 103     ps.vdd("E", ('E', 25), 0, 5, 1)
 104     ps.gpio("", ('E', 26), 0, 14, 4) # GPIO 14-17
 105     ps.rgmii("1", ('E', 26), 1, 14, 5) # more RGMII-2
 106     ps.eint("", ('E', 28), 2, 0, 2)
 107     ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
 108
 109     ps.gpio("", ('N', 0), 0, 0, 4) # GPIO 0-3
 110     ps.rgmii("0", ('N', 0), 1, 0, 4) # RXD0-3
 111     ps.vss("E", ('N', 4), 0, 6, 1)
 112     ps.vdd("E", ('N', 5), 0, 6, 1)
 113     ps.vdd("I", ('N', 6), 0, 6, 1)
 114     ps.vss("I", ('N', 7), 0, 6, 1)
 115     ps.gpio("", ('N', 8), 0, 4, 14) # GPIO 4-17
 116     ps.rgmii("0", ('N', 8), 1, 4, 14) # more RGMII-1
 117     #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
 118     #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
 119     #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
 120     ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
 121     ps.vss("I", ('N', 23), 0, 7, 1)
 122     ps.vdd("I", ('N', 24), 0, 7, 1)
 123     ps.vss("E", ('N', 25), 0, 7, 1)
 124     ps.vdd("E", ('N', 26), 0, 7, 1)
 125
 126     #ps.mquadspi("1", ('S', 0), 0)
 127
 128     print ("ps clocks", ps.clocks)
 129
 130     # Scenarios below can be spec'd out as either "find first interface"
 131     # by name/number e.g. SPI1, or as "find in bank/mux" which must be
 132     # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
 133     # EINT and PWM are grouped together, specially, but may still be spec'd
 134     # using "BM:Name".  Pins are removed in-order as listed from
 135     # lists (interfaces, EINTs, PWMs) from available pins.
 136
 137     ls180 = [
 138             # 'SD0', litex problem 25mar2021
 139             'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
 140              'VDD', 'VSS', 'SYS',
 141                 'MTWI', 'MSPI0',
 142                 # 'MSPI1', litex problem 25mar2021
 143                 'SDR']
 144     ls180_eint = []
 145     ls180_pwm = []#['B0:PWM_0']
 146     descriptions = {
 147         'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
 148         'and UART2, for debug purposes',
 149         'MTWI': 'I2C.\n',
 150         'E2:SD1': '',
 151         'MSPI1': '',
 152         'UART0': '',
 153         'LPC1': '',
 154         'SYS': '',
 155         'LPC2': '',
 156         'SDR': '',
 157         'B1:LCD/22': '18-bit RGB/TTL LCD',
 158         'ULPI0/8': 'user-facing: internal (on Card), USB-OTG ULPI PHY',
 159         'ULPI1': 'dual USB2 Host ULPI PHY'
 160     }
 161
 162     ps.add_scenario("Libre-SOC 2 (NGI Router) 180nm", ls180, ls180_eint,
 163                     ls180_pwm, descriptions)
 164
 165     return ps