src/spec/ls2.py

   1 #!/usr/bin/env python
   2 # see https://bugs.libre-soc.org/show_bug.cgi?id=739
   3
   4 from spec.base import PinSpec
   5 from parse import Parse
   6
   7 from pprint import pprint
   8 from spec.ifaceprint import display, display_fns, check_functions
   9 from spec.ifaceprint import display_fixed
  10 from collections import OrderedDict
  11
  12 def pinspec():
  13     pinbanks = OrderedDict((
  14         ('N', (32, 4)),
  15         ('E', (32, 4)),
  16         ('S', (32, 4)),
  17         ('W', (32, 4)),
  18     ))
  19     fixedpins = {
  20         'CTRL_SYS': [
  21             'TEST',
  22             'JTAG_SEL',
  23             'UBOOT_SEL',
  24             'NMI#',
  25             'RESET#',
  26             'CLK24M_IN',
  27             'CLK24M_OUT',
  28             'PLLTEST',
  29             'PLLREGIO',
  30             'PLLVP25',
  31             'PLLDV',
  32             'PLLVREG',
  33             'PLLGND',
  34         ],
  35         'POWER_GPIO': [
  36             'VDD_GPIOB',
  37             'GND_GPIOB',
  38         ]}
  39     fixedpins = {}
  40     function_names = {
  41                       'RG0': 'Gigabit Ethernet 0',
  42                       'PWM': 'PWM (pulse-width modulation)',
  43                       'MSPI0': 'SPI Master 1 (general)',
  44                       'MSPI1': 'SPI Master 2 (SDCard)',
  45                       'UART0': 'UART (TX/RX) 1',
  46                       'SYS': 'System Control',
  47                       'GPIO': 'GPIO',
  48                       'EINT': 'External Interrupt',
  49                       'PWM': 'PWM',
  50                       'JTAG': 'JTAG',
  51                       'MTWI': 'I2C Master 1',
  52                       'SD0': 'SD/MMC 1',
  53                       'SDR': 'SDRAM',
  54                       'VDD': 'Power',
  55                       'VSS': 'GND',
  56                       #'LPC1': 'Low Pincount Interface 1',
  57                       #'LPC2': 'Low Pincount Interface 2',
  58                       }
  59
  60     ps = PinSpec(pinbanks, fixedpins, function_names)
  61
  62     ps.gpio("", ('W', 0), 0, 0, 6) # GPIO 0-5
  63     ps.sdram1("", ('W', 0), 1, 15, 6, rev=True) # AD4-9, turned round
  64     ps.vdd("E", ('W', 6), 0, 0, 1)
  65     ps.vss("E", ('W', 7), 0, 0, 1)
  66     ps.vdd("I", ('W', 8), 0, 0, 1)
  67     ps.vss("I", ('W', 9), 0, 0, 1)
  68     ps.gpio("", ('W', 10), 0, 6, 18) # GPIO 6-23
  69     ps.sdram1("", ('W', 10), 1, 0, 15, rev=True) # SDRAM DAM0, D0-7, AD0-3
  70     ps.mi2c("", ('W', 26), 1, 0, 2)
  71     ps.vss("I", ('W', 28), 0, 1, 1)
  72     ps.vdd("I", ('W', 29), 0, 1, 1)
  73     ps.vss("E", ('W', 30), 0, 1, 1)
  74     ps.vdd("E", ('W', 31), 0, 1, 1)
  75
  76     ps.gpio("", ('S', 0), 0, 0, 4) # GPIO 0-4
  77     ps.sdram2("", ('S', 0), 1, 0, 4) # 1st 4, AD10-12,DQM1
  78     ps.vdd("E", ('S', 4), 0, 2, 1)
  79     ps.vss("E", ('S', 5), 0, 2, 1)
  80     ps.vdd("I", ('S', 6), 0, 2, 1)
  81     ps.vss("I", ('S', 7), 0, 2, 1)
  82     ps.gpio("", ('S', 8), 0, 4, 14) # GPIO 5-17
  83     ps.sdram2("", ('S', 8), 1, 4, 8) # D8-15
  84     ps.sdram1("", ('S', 16), 1, 21, 9) # clk etc.
  85     ps.vss("I", ('S', 22), 0, 3, 1)
  86     ps.vdd("I", ('S', 23), 0, 3, 1)
  87     ps.vss("E", ('S', 24), 0, 3, 1)
  88     ps.vdd("E", ('S', 25), 0, 3, 1)
  89     ps.gpio("", ('S', 26), 0, 18, 6) # GPIO 18-23
  90     ps.uart("0", ('S', 26), 1)
  91     ps.mspi("0", ('S', 28), 1)
  92
  93     ps.gpio("", ('E', 0), 0, 0, 4) # GPIO 0-3
  94     ps.rgmii("1", ('E', 0), 1, 0, 4) # RXD0-3
  95     ps.vss("E", ('E', 4), 0, 4, 1)
  96     ps.vdd("E", ('E', 5), 0, 4, 1)
  97     ps.vdd("I", ('E', 6), 0, 4, 1)
  98     ps.vss("I", ('E', 7), 0, 4, 1)
  99     ps.gpio("", ('E', 8), 0, 6, 10) # GPIO 4-13
 100     ps.rgmii("1", ('E', 8), 1, 4, 10) # more RGMII-2
 101     ps.jtag("", ('E', 18), 0, 0, 4)
 102     ps.vss("I", ('E', 22), 0, 5, 1)
 103     ps.vdd("I", ('E', 23), 0, 5, 1)
 104     ps.vss("E", ('E', 24), 0, 5, 1)
 105     ps.vdd("E", ('E', 25), 0, 5, 1)
 106     ps.gpio("", ('E', 26), 0, 16, 5) # GPIO 14-18
 107     ps.rgmii("1", ('E', 26), 1, 14, 5) # more RGMII-2
 108     ps.eint("", ('E', 28), 2, 0, 3)
 109     ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
 110
 111     ps.gpio("", ('N', 0), 0, 0, 4) # GPIO 0-3
 112     ps.rgmii("0", ('N', 0), 1, 0, 4) # RXD0-3
 113     ps.vss("E", ('N', 4), 0, 6, 1)
 114     ps.vdd("E", ('N', 5), 0, 6, 1)
 115     ps.vdd("I", ('N', 6), 0, 6, 1)
 116     ps.vss("I", ('N', 7), 0, 6, 1)
 117     ps.gpio("", ('N', 8), 0, 4, 14) # GPIO 4-17
 118     ps.rgmii("0", ('N', 8), 1, 4, 14) # more RGMII-1
 119     #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
 120     #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
 121     #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
 122     ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
 123     ps.vss("I", ('N', 23), 0, 7, 1)
 124     ps.vdd("I", ('N', 24), 0, 7, 1)
 125     ps.vss("E", ('N', 25), 0, 7, 1)
 126     ps.vdd("E", ('N', 26), 0, 7, 1)
 127
 128     #ps.mquadspi("1", ('S', 0), 0)
 129
 130     print ("ps clocks", ps.clocks)
 131
 132     # Scenarios below can be spec'd out as either "find first interface"
 133     # by name/number e.g. SPI1, or as "find in bank/mux" which must be
 134     # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
 135     # EINT and PWM are grouped together, specially, but may still be spec'd
 136     # using "BM:Name".  Pins are removed in-order as listed from
 137     # lists (interfaces, EINTs, PWMs) from available pins.
 138
 139     ls180 = [
 140             # 'SD0', litex problem 25mar2021
 141             'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
 142              'VDD', 'VSS', 'SYS',
 143                 'MTWI', 'MSPI0',
 144                 'RG0', 'RG1',
 145                 # 'MSPI1', litex problem 25mar2021
 146                 'SDR']
 147     ls180_eint = []
 148     ls180_pwm = []#['B0:PWM_0']
 149     descriptions = {
 150         'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
 151         'and UART2, for debug purposes',
 152         'MTWI': 'I2C.\n',
 153         'E2:SD1': '',
 154         'MSPI1': '',
 155         'UART0': '',
 156         'LPC1': '',
 157         'RG0': '',
 158         'RG1': '',
 159         'SYS': '',
 160         'LPC2': '',
 161         'SDR': '',
 162         'B1:LCD/22': '18-bit RGB/TTL LCD',
 163         'ULPI0/8': 'user-facing: internal (on Card), USB-OTG ULPI PHY',
 164         'ULPI1': 'dual USB2 Host ULPI PHY'
 165     }
 166
 167     ps.add_scenario("Libre-SOC 2 (NGI Router) 180nm", ls180, ls180_eint,
 168                     ls180_pwm, descriptions)
 169
 170     return ps