src/spec/pinfunctions.py

   1 #!/usr/bin/env python
   2
   3 """ define functions here, with their pin names and the pin type.
   4
   5     each function returns a pair of lists
   6     (or objects with a __getitem__ function)
   7
   8     the first list (or object) contains pin name plus type specifications.
   9
  10     the type is:
  11
  12     * "-" for an input pin,
  13     * "+" for an output pin,
  14     * "*" for an in/out pin
  15
  16     each function is then added to the pinspec tuple, below, as a ("NAME",
  17     function) entry.
  18
  19     different functions may be added multiple times under the same NAME,
  20     so that complex (or large) functions can be split into one or more
  21     groups (and placed on different pinbanks).
  22
  23     eint, pwm and gpio are slightly odd in that instead of a fixed list
  24     an object is returned with a __getitem__ function that accepts a
  25     slice object.  in this way the actual generation of the pin name
  26     is delayed until it is known precisely how many pins are to be
  27     generated, and that's not known immediately (or it would be if
  28     every single one of the functions below had a start and end parameter
  29     added).  see spec.interfaces.PinGen class slice on pingroup
  30
  31     the second list is the names of pins that are part of an inout bus.
  32     this list of pins (a ganged group) will need to be changed under
  33     the control of the function, as a group.  for example: sdmmc's
  34     D0-D3 pins are in-out, they all change from input to output at
  35     the same time under the control of the function, therefore there's
  36     no point having multiple in-out switch/control wires, as the
  37     sdmmc is never going to do anything other than switch this entire
  38     bank all at once.  so in this particular example, sdmmc returns:
  39
  40     (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
  41      ['D0*', 'D1*', 'D2*', 'D3*'])                # ganged bus names
  42
  43     addition:
  44
  45     3rd item in list gives the name of the clock.
  46 """
  47
  48
  49 def i2s(suffix, bank):
  50     return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
  51             [])
  52
  53
  54 # XXX TODO: correct these.  this is a stub for now
  55 # https://bugs.libre-soc.org/show_bug.cgi?id=303
  56 def lpc(suffix, bank, pincount=4):
  57     lpcpins = ['CMD+', 'CLK+']
  58     inout = []
  59     for i in range(pincount):
  60         pname = "D%d*" % i
  61         lpcpins.append(pname)
  62         inout.append(pname)
  63     return (lpcpins, inout, 'CLK')
  64
  65
  66 def emmc(suffix, bank, pincount=8):
  67     emmcpins = ['CMD+', 'CLK+']
  68     inout = []
  69     for i in range(pincount):
  70         pname = "D%d*" % i
  71         emmcpins.append(pname)
  72         inout.append(pname)
  73     return (emmcpins, inout, 'CLK')
  74
  75
  76 def sdmmc(suffix, bank):
  77     return emmc(suffix, bank, pincount=4)
  78
  79
  80 def nspi(suffix, bank, iosize, masteronly=True):
  81     if masteronly:
  82         qpins = ['CK+', 'NSS+']
  83     else:
  84         qpins = ['CK*', 'NSS*']
  85     inout = []
  86     if iosize == 2:
  87         qpins += ['MOSI+', 'MISO-']
  88     else:
  89         for i in range(iosize):
  90             pname = "IO%d*" % i
  91             qpins.append(pname)
  92             inout.append(pname)
  93     return (qpins, inout, 'CK')
  94
  95
  96 def mspi(suffix, bank):
  97     return nspi(suffix, bank, 2, masteronly=True)
  98
  99
 100 def mquadspi(suffix, bank):
 101     return nspi(suffix, bank, 4, masteronly=True)
 102
 103
 104 def spi(suffix, bank):
 105     return nspi(suffix, bank, 2)
 106
 107
 108 def quadspi(suffix, bank):
 109     return nspi(suffix, bank, 4)
 110
 111
 112 def i2c(suffix, bank):
 113     return (['SDA*', 'SCL*'], [], 'SCL')
 114
 115
 116 def jtag(suffix, bank):
 117     return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [], 'TCK')
 118
 119
 120 def uart(suffix, bank):
 121     return (['TX+', 'RX-'], [], None)
 122
 123
 124 def ulpi(suffix, bank):
 125     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 126     for i in range(8):
 127         ulpipins.append('D%d*' % i)
 128     return (ulpipins, [], 'CK')
 129
 130
 131 def uartfull(suffix, bank):
 132     return (['TX+', 'RX-', 'CTS-', 'RTS+'], [], None)
 133
 134
 135 def rgbttl(suffix, bank):
 136     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 137     for i in range(24):
 138         ttlpins.append("OUT%d+" % i)
 139     return (ttlpins, [], 'CK')
 140
 141
 142 def rgmii(suffix, bank):
 143     buspins = []
 144     for i in range(4):
 145         buspins.append("ERXD%d-" % i)
 146     for i in range(4):
 147         buspins.append("ETXD%d+" % i)
 148     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 149                 'EMDC+', 'EMDIO*',
 150                 'ETXEN+', 'ETXCK+', 'ECRS-',
 151                 'ECOL+', 'ETXERR+']
 152     return (buspins, [], ['ERXCK', 'ETXCK'])
 153
 154
 155 def flexbus1(suffix, bank):
 156     buspins = []
 157     inout = []
 158     for i in range(8):
 159         pname = "AD%d*" % i
 160         buspins.append(pname)
 161         inout.append(pname)
 162     for i in range(2):
 163         buspins.append("CS%d+" % i)
 164     buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
 165                 # 'TS+',  commented out for now, mirrors ALE, for mux'd mode
 166                 'TBST+',
 167                 'TSIZ0+', 'TSIZ1+']
 168     for i in range(4):
 169         buspins.append("BWE%d+" % i)
 170     for i in range(2, 6):
 171         buspins.append("CS%d+" % i)
 172     return (buspins, inout, None)
 173
 174
 175 def flexbus2(suffix, bank):
 176     buspins = []
 177     for i in range(8, 32):
 178         buspins.append("AD%d*" % i)
 179     return (buspins, buspins, None)
 180
 181
 182 def sdram1(suffix, bank, n_adr=10):
 183     buspins = []
 184     inout = []
 185     for i in range(1):
 186         pname = "DQM%d+" % i
 187         buspins.append(pname)
 188     for i in range(8):
 189         pname = "D%d*" % i
 190         buspins.append(pname)
 191         inout.append(pname)
 192     for i in range(n_adr):
 193         buspins.append("AD%d+" % i)
 194     for i in range(2):
 195         buspins.append("BA%d+" % i)
 196     buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
 197                 'CSn0+']
 198     return (buspins, inout, 'CLK')
 199
 200
 201 def sdram2(suffix, bank):
 202     buspins = []
 203     inout = []
 204     for i in range(10, 13):
 205         buspins.append("AD%d+" % i)
 206     for i in range(1, 2):
 207         pname = "DQM%d*" % i
 208         buspins.append(pname)
 209     for i in range(8, 16):
 210         pname = "D%d*" % i
 211         buspins.append(pname)
 212         inout.append(pname)
 213     return (buspins, inout, None)
 214
 215
 216 def sdram3(suffix, bank):
 217     buspins = []
 218     inout = []
 219     for i in range(1, 6):
 220         buspins.append("CSn%d+" % i)
 221     for i in range(13, 14):
 222         buspins.append("AD%d+" % i)
 223     for i in range(1, 4):
 224         pname = "DQM%d*" % i
 225     for i in range(8, 32):
 226         pname = "D%d*" % i
 227         buspins.append(pname)
 228         inout.append(pname)
 229     return (buspins, inout, None)
 230
 231
 232 def mcu8080(suffix, bank):
 233     buspins = []
 234     inout = []
 235     for i in range(8):
 236         pname = "D%d*" % i
 237         buspins.append(pname)
 238         inout.append(pname)
 239     for i in range(8):
 240         buspins.append("AD%d+" % (i + 8))
 241     for i in range(6):
 242         buspins.append("CS%d+" % i)
 243     for i in range(2):
 244         buspins.append("NRB%d+" % i)
 245     buspins += ['CD+', 'RD+', 'WR+', 'CLE+', 'ALE+',
 246                 'RST+']
 247     return (buspins, inout, None)
 248
 249
 250 class RangePin(object):
 251     def __init__(self, suffix, prefix=None):
 252         self.suffix = suffix
 253         self.prefix = prefix or ''
 254
 255     def __getitem__(self, s):
 256         res = []
 257         for idx in range(s.start or 0, s.stop or -1, s.step or 1):
 258             res.append("%s%d%s" % (self.prefix, idx, self.suffix))
 259         return res
 260
 261
 262 def eint(suffix, bank):
 263     return (RangePin("-"), [], None)
 264
 265
 266 def pwm(suffix, bank):
 267     return (RangePin("+"), [], None)
 268
 269
 270 def gpio(suffix, bank):
 271     return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [], None)
 272
 273 def vss(suffix, bank):
 274     return (RangePin("-"), [], None)
 275
 276 def vdd(suffix, bank):
 277     return (RangePin("-"), [], None)
 278
 279 def sys(suffix, bank):
 280     return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
 281              'CSEL0-', 'CSEL1-', 'CSEL2-'], [], 'CLK')
 282
 283 # list functions by name here
 284
 285 pinspec = (('IIS', i2s),
 286            ('LPC', lpc),
 287            ('EMMC', emmc),
 288            ('SD', sdmmc),
 289            ('MSPI', mspi),
 290            ('MQSPI', mquadspi),
 291            ('SPI', spi),
 292            ('QSPI', quadspi),
 293            ('TWI', i2c),
 294            ('JTAG', jtag),
 295            ('UART', uart),
 296            ('QUART', uartfull),
 297            ('LCD', rgbttl),
 298            ('ULPI', ulpi),
 299            ('RG', rgmii),
 300            ('FB', flexbus1),
 301            ('FB', flexbus2),
 302            ('SDR', sdram1),
 303            ('SDR', sdram2),
 304            ('SDR', sdram3),
 305            ('VSS', vss),
 306            ('VDD', vdd),
 307            ('SYS', sys),
 308            ('EINT', eint),
 309            ('PWM', pwm),
 310            ('GPIO', gpio),
 311            )