3 """ define functions here, with their pin names and the pin type.
5 each function returns a list (or an object with a __getitem__ function)
6 containing pin name plus type specifications.
10 * "-" for an input pin,
11 * "+" for an output pin,
12 * "*" for an in/out pin
14 each function is then added to the pinspec tuple, below, as a ("NAME",
17 different functions may be added multiple times under the same NAME,
18 so that complex (or large) functions can be split into one or more
19 groups (and placed on different pinbanks).
21 eint, pwm and gpio are slightly odd in that instead of a fixed list
22 an object is returned with a __getitem__ function that accepts a
23 slice object. in this way the actual generation of the pin name
24 is delayed until it is known precisely how many pins are to be
25 generated, and that's not known immediately (or it would be if
26 every single one of the functions below had a start and end parameter
27 added). see spec.interfaces.PinGen class slice on pingroup
30 def i2s(suffix
, bank
):
31 return ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
33 def emmc(suffix
, bank
):
34 emmcpins
= ['CMD+', 'CLK+']
36 emmcpins
.append("D%d*" % i
)
39 def sdmmc(suffix
, bank
):
40 sdmmcpins
= ['CMD+', 'CLK+']
42 sdmmcpins
.append("D%d*" % i
)
45 def spi(suffix
, bank
):
46 return ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
48 def quadspi(suffix
, bank
):
49 return ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
51 def i2c(suffix
, bank
):
52 return ['SDA*', 'SCL*']
54 def jtag(suffix
, bank
):
55 return ['MS+', 'DI-', 'DO+', 'CK+']
57 def uart(suffix
, bank
):
60 def ulpi(suffix
, bank
):
61 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
63 ulpipins
.append('D%d*' % i
)
66 def uartfull(suffix
, bank
):
67 return ['TX+', 'RX-', 'CTS-', 'RTS+']
69 def rgbttl(suffix
, bank
):
70 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
72 ttlpins
.append("D%d+" % i
)
75 def rgmii(suffix
, bank
):
78 buspins
.append("ERXD%d-" % i
)
80 buspins
.append("ETXD%d+" % i
)
81 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
83 'ETXEN+', 'ETXCK+', 'ECRS-',
87 def flexbus1(suffix
, bank
):
90 buspins
.append("AD%d*" % i
)
92 buspins
.append("CS%d+" % i
)
93 buspins
+= ['ALE', 'OE', 'RW', 'TA', 'CLK+',
94 'A0', 'A1', 'TS', 'TBST',
97 buspins
.append("BWE%d" % i
)
99 buspins
.append("CS%d+" % i
)
102 def flexbus2(suffix
, bank
):
104 for i
in range(8, 32):
105 buspins
.append("AD%d*" % i
)
108 def sdram1(suffix
, bank
):
111 buspins
.append("SDRDQM%d*" % i
)
113 buspins
.append("SDRAD%d+" % i
)
115 buspins
.append("SDRDQ%d+" % i
)
117 buspins
.append("SDRCS%d#+" % i
)
119 buspins
.append("SDRDQ%d+" % i
)
121 buspins
.append("SDRBA%d+" % i
)
122 buspins
+= ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
126 def sdram2(suffix
, bank
):
128 for i
in range(3, 6):
129 buspins
.append("SDRCS%d#+" % i
)
130 for i
in range(8, 32):
131 buspins
.append("SDRDQ%d*" % i
)
134 def mcu8080(suffix
, bank
):
137 buspins
.append("MCUD%d*" % i
)
139 buspins
.append("MCUAD%d+" % (i
+ 8))
141 buspins
.append("MCUCS%d+" % i
)
143 buspins
.append("MCUNRB%d+" % i
)
144 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
148 class RangePin(object):
149 def __init__(self
, suffix
, prefix
=None):
151 self
.prefix
= prefix
or ''
153 def __getitem__(self
, s
):
155 for idx
in range(s
.start
or 0, s
.stop
or -1, s
.step
or 1):
156 res
.append("%s%d%s" % (self
.prefix
, idx
, self
.suffix
))
159 def eint(suffix
, bank
):
162 def pwm(suffix
, bank
):
165 def gpio(suffix
, bank
):
166 return ("GPIO%s" % bank
, RangePin(prefix
=bank
, suffix
="*"))
169 # list functions by name here
171 pinspec
= (('IIS', i2s
),