3 """ define functions here, with their pin names and the pin type.
5 each function returns a pair of lists
6 (or objects with a __getitem__ function)
8 the first list (or object) contains pin name plus type specifications.
12 * "-" for an input pin,
13 * "+" for an output pin,
14 * "*" for an in/out pin
16 each function is then added to the pinspec tuple, below, as a ("NAME",
19 different functions may be added multiple times under the same NAME,
20 so that complex (or large) functions can be split into one or more
21 groups (and placed on different pinbanks).
23 eint, pwm and gpio are slightly odd in that instead of a fixed list
24 an object is returned with a __getitem__ function that accepts a
25 slice object. in this way the actual generation of the pin name
26 is delayed until it is known precisely how many pins are to be
27 generated, and that's not known immediately (or it would be if
28 every single one of the functions below had a start and end parameter
29 added). see spec.interfaces.PinGen class slice on pingroup
31 the second list is the names of pins that are part of an inout bus.
32 this list of pins (a ganged group) will need to be changed under
33 the control of the function, as a group. for example: sdmmc's
34 D0-D3 pins are in-out, they all change from input to output at
35 the same time under the control of the function, therefore there's
36 no point having multiple in-out switch/control wires, as the
37 sdmmc is never going to do anything other than switch this entire
38 bank all at once. so in this particular example, sdmmc returns:
40 (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
41 ['D0*', 'D1*', 'D2*', 'D3*']) # ganged bus names
45 def i2s(suffix
, bank
):
46 return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
50 # XXX TODO: correct these. this is a stub for now
51 # https://bugs.libre-soc.org/show_bug.cgi?id=303
52 def lpc(suffix
, bank
, pincount
=4):
53 lpcpins
= ['CMD+', 'CLK+']
55 for i
in range(pincount
):
59 return (lpcpins
, inout
)
62 def emmc(suffix
, bank
, pincount
=8):
63 emmcpins
= ['CMD+', 'CLK+']
65 for i
in range(pincount
):
67 emmcpins
.append(pname
)
69 return (emmcpins
, inout
)
72 def sdmmc(suffix
, bank
):
73 return emmc(suffix
, bank
, pincount
=4)
76 def nspi(suffix
, bank
, iosize
, masteronly
=True):
78 qpins
= ['CK+', 'NSS+']
80 qpins
= ['CK*', 'NSS*']
83 qpins
+= ['MOSI+', 'MISO-']
85 for i
in range(iosize
):
92 def mspi(suffix
, bank
):
93 return nspi(suffix
, bank
, 2, masteronly
=True)
96 def mquadspi(suffix
, bank
):
97 return nspi(suffix
, bank
, 4, masteronly
=True)
100 def spi(suffix
, bank
):
101 return nspi(suffix
, bank
, 2)
104 def quadspi(suffix
, bank
):
105 return nspi(suffix
, bank
, 4)
108 def i2c(suffix
, bank
):
109 return (['SDA*', 'SCL*'], [])
112 def jtag(suffix
, bank
):
113 return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
116 def uart(suffix
, bank
):
117 return (['TX+', 'RX-'], [])
120 def ulpi(suffix
, bank
):
121 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
123 ulpipins
.append('D%d*' % i
)
124 return (ulpipins
, [])
127 def uartfull(suffix
, bank
):
128 return (['TX+', 'RX-', 'CTS-', 'RTS+'],
132 def rgbttl(suffix
, bank
):
133 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
135 ttlpins
.append("OUT%d+" % i
)
139 def rgmii(suffix
, bank
):
142 buspins
.append("ERXD%d-" % i
)
144 buspins
.append("ETXD%d+" % i
)
145 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
147 'ETXEN+', 'ETXCK+', 'ECRS-',
152 def flexbus1(suffix
, bank
):
157 buspins
.append(pname
)
160 buspins
.append("CS%d+" % i
)
161 buspins
+= ['ALE+', 'OE+', 'RW+', 'TA-',
162 # 'TS+', commented out for now, mirrors ALE, for mux'd mode
166 buspins
.append("BWE%d+" % i
)
167 for i
in range(2, 6):
168 buspins
.append("CS%d+" % i
)
169 return (buspins
, inout
)
172 def flexbus2(suffix
, bank
):
174 for i
in range(8, 32):
175 buspins
.append("AD%d*" % i
)
176 return (buspins
, buspins
)
179 def sdram1(suffix
, bank
, n_adr
=10):
184 buspins
.append(pname
)
187 buspins
.append(pname
)
189 for i
in range(n_adr
):
190 buspins
.append("AD%d+" % i
)
192 buspins
.append("BA%d+" % i
)
193 buspins
+= ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
195 return (buspins
, inout
)
198 def sdram2(suffix
, bank
):
201 for i
in range(10, 13):
202 buspins
.append("SDRAD%d+" % i
)
203 for i
in range(1, 2):
205 buspins
.append(pname
)
206 for i
in range(8, 16):
208 buspins
.append(pname
)
210 return (buspins
, inout
)
213 def sdram3(suffix
, bank
):
216 for i
in range(1, 6):
217 buspins
.append("CSn%d+" % i
)
218 for i
in range(13, 14):
219 buspins
.append("SDRAD%d+" % i
)
220 for i
in range(1, 4):
222 for i
in range(8, 32):
223 pname
= "SDRD%d*" % i
224 buspins
.append(pname
)
226 return (buspins
, inout
)
229 def mcu8080(suffix
, bank
):
233 pname
= "MCUD%d*" % i
234 buspins
.append(pname
)
237 buspins
.append("MCUAD%d+" % (i
+ 8))
239 buspins
.append("MCUCS%d+" % i
)
241 buspins
.append("MCUNRB%d+" % i
)
242 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
244 return (buspins
, inout
)
247 class RangePin(object):
248 def __init__(self
, suffix
, prefix
=None):
250 self
.prefix
= prefix
or ''
252 def __getitem__(self
, s
):
254 for idx
in range(s
.start
or 0, s
.stop
or -1, s
.step
or 1):
255 res
.append("%s%d%s" % (self
.prefix
, idx
, self
.suffix
))
259 def eint(suffix
, bank
):
260 return (RangePin("-"), [])
263 def pwm(suffix
, bank
):
264 return (RangePin("+"), [])
267 def gpio(suffix
, bank
):
268 return (("GPIO%s" % bank
, RangePin(prefix
=bank
, suffix
="*")), [])
270 def vss(suffix
, bank
):
271 return (RangePin("-"), [])
273 def vdd(suffix
, bank
):
274 return (RangePin("-"), [])
276 def clk(suffix
, bank
):
277 return (RangePin("-"), [])
279 def rst(suffix
, bank
):
280 return (RangePin("-"), [])
282 # list functions by name here
284 pinspec
= (('IIS', i2s
),