src/spec/pinmux.py

   1 """
   2 1-bit pinmux case
   3
   4 """
   5 from random import randint
   6 #from math import ceil, floor
   7 from nmigen import Elaboratable, Module, Signal, Record, Array, Cat
   8 from nmigen.hdl.rec import Layout
   9 from nmigen.utils import log2_int
  10 from nmigen.cli import rtlil
  11 #from soc.minerva.wishbone import make_wb_layout
  12 from nmutil.util import wrap
  13 #from soc.bus.test.wb_rw import wb_read, wb_write
  14
  15 from nmutil.gtkw import write_gtkw
  16
  17 cxxsim = False
  18 if cxxsim:
  19     from nmigen.sim.cxxsim import Simulator, Settle, Delay
  20 else:
  21     from nmigen.sim import Simulator, Settle, Delay
  22
  23 from iomux import IOMuxBlockSingle, io_layout
  24 from simple_gpio import SimpleGPIO
  25
  26 class PinMuxBlockSingle(Elaboratable):
  27
  28     def __init__(self):
  29         print("1-bit Pin Mux Block with JTAG")
  30         self.n_banks = 4
  31         self.bank = Signal(log2_int(self.n_banks))
  32         self.n_gpios = 1
  33         self.wb_wordsize = 4 # 4 Bytes, 32-bits
  34
  35         temp = []
  36         for i in range(1, self.n_banks):
  37             temp_str = "periph{}".format(i)
  38             temp.append(Record(name=temp_str, layout=io_layout))
  39         self.periph_ports = Array(temp)
  40
  41         self.out_port = Record(name="IO", layout=io_layout)
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45         comb, sync = m.d.comb, m.d.sync
  46         iomux = IOMuxBlockSingle()
  47         gpio = SimpleGPIO(self.wb_wordsize, self.n_gpios)
  48         m.submodules.iomux += iomux
  49         m.submodules.gpio += gpio
  50
  51         bank = self.bank
  52         periph_ports = self.periph_ports
  53         out_port = self.out_port
  54
  55         # Connect up modules and signals
  56         iomux.bank.eq(gpio.gpio_ports[0].bank)
  57
  58         # WB GPIO always bank0
  59         gpio.gpio_ports[0].o.eq(iomux.bank_ports[0].o)
  60         gpio.gpio_ports[0].oe.eq(iomux.bank_ports[0].oe)
  61         iomux.bank_ports[0].i.eq(gpio.gpio_ports[0].i)
  62
  63         # banks1-3 external
  64         for bank in range(0, self.n_banks-1):
  65             periph_ports[bank].o.eq(iomux.bank_ports[bank+1].o)
  66             periph_ports[bank].oe.eq(iomux.bank_ports[bank+1].oe)
  67             iomux.bank_ports[bank+1].i.eq(periph_ports[bank].i)
  68
  69         out_port.o.eq(iomux.out_port.o)
  70         out_port.oe.eq(iomux.out_port.oe)
  71         iomux.out_port.i.eq(out_port.i)
  72
  73         return m
  74
  75     def __iter__(self):
  76         """ Get member signals for Verilog form. """
  77         for field in self.out_port.fields.values():
  78             yield field
  79         for bank in range(len(self.periph_ports)):
  80             for field in self.periph_ports[bank].fields.values():
  81                 yield field
  82         #yield self.bank
  83
  84     def ports(self):
  85         return list(self)
  86
  87 def gen_gtkw_doc(module_name, n_banks, filename):
  88     # GTKWave doc generation
  89     style = {
  90         '': {'base': 'hex'},
  91         'in': {'color': 'orange'},
  92         'out': {'color': 'yellow'},
  93         'debug': {'module': 'top', 'color': 'red'}
  94     }
  95
  96     # Create a trace list, each block expected to be a tuple()
  97     traces = []
  98     for bank in range(0, n_banks):
  99         temp_traces = ('Bank{}'.format(bank), [
 100                         ('bank{}__i'.format(bank), 'in'),
 101                         ('bank{}__o'.format(bank), 'out'),
 102                         ('bank{}__oe'.format(bank), 'out')
 103                       ])
 104         traces.append(temp_traces)
 105
 106     temp_traces = ('Misc', [
 107                     ('bank[1:0]', 'in')
 108                   ])
 109     traces.append(temp_traces)
 110     temp_traces = ('IO port to pad', [
 111                     ('IO__i', 'in'),
 112                     ('IO__o', 'out'),
 113                     ('IO__oe', 'out')
 114                   ])
 115     traces.append(temp_traces)
 116     #print(traces)
 117
 118     write_gtkw(filename+".gtkw", filename+".vcd", traces, style,
 119                module=module_name)
 120
 121 def sim_iomux():
 122     filename = "test_pinmux" # Doesn't include extension
 123     dut = PinMuxBlockSingle()
 124     vl = rtlil.convert(dut, ports=dut.ports())
 125     with open(filename+".il", "w") as f:
 126         f.write(vl)
 127
 128     #m = Module()
 129     #m.submodules.pinmux = dut
 130
 131     #sim = Simulator(m)
 132
 133     #sim.add_process(wrap(test_iomux(dut)))
 134     #sim_writer = sim.write_vcd(filename+".vcd")
 135     #with sim_writer:
 136     #    sim.run()
 137
 138     #gen_gtkw_doc("top.pinmux", dut.n_banks, filename)
 139
 140 def test_iomux(dut):
 141     print("------START----------------------")
 142     #print(dir(dut.bank_ports[0]))
 143     #print(dut.bank_ports[0].fields)
 144
 145     # TODO: turn into methods
 146     yield from test_single_bank(dut, 0)
 147     yield from test_single_bank(dut, 1)
 148     yield from test_single_bank(dut, 2)
 149     yield from test_single_bank(dut, 3)
 150
 151     print("Finished the 1-bit IO mux block test!")
 152
 153 if __name__ == '__main__':
 154     sim_iomux()
 155