src/spec/simple_gpio.py

   1 """Simple GPIO peripheral on wishbone
   2
   3 This is an extremely simple GPIO peripheral intended for use in XICS
   4 testing, however it could also be used as an actual GPIO peripheral
   5
   6 Modified for use with pinmux, will probably change the class name later.
   7 """
   8 from random import randint
   9 from math import ceil, floor
  10 from nmigen import Elaboratable, Module, Signal, Record, Array, Cat, Const
  11 from nmigen.hdl.rec import Layout
  12 from nmigen.utils import log2_int
  13 from nmigen.cli import rtlil
  14 from soc.minerva.wishbone import make_wb_layout
  15 from nmutil.util import wrap
  16 from soc.bus.test.wb_rw import wb_read, wb_write
  17
  18 from nmutil.gtkw import write_gtkw
  19
  20 cxxsim = False
  21 if cxxsim:
  22     from nmigen.sim.cxxsim import Simulator, Settle
  23 else:
  24     from nmigen.sim import Simulator, Settle
  25
  26 # Layout of 8-bit configuration word:
  27 # bank[2:0] i/o | pden puen ien oe
  28 NUMBANKBITS = 3 # max 3 bits, only supporting 4 banks (0-3)
  29 csrbus_layout = (("oe", 1),
  30                  ("ie", 1),
  31                  ("puen", 1),
  32                  ("pden", 1),
  33                  ("io", 1),
  34                  ("bank", NUMBANKBITS)
  35                 )
  36
  37 gpio_layout = (("i", 1),
  38                ("oe", 1),
  39                ("o", 1),
  40                ("puen", 1),
  41                ("pden", 1),
  42                ("bank", NUMBANKBITS)
  43               )
  44
  45 class SimpleGPIO(Elaboratable):
  46
  47     def __init__(self, wordsize=4, n_gpio=16):
  48         self.wordsize = wordsize
  49         self.n_gpio = n_gpio
  50         self.n_rows = ceil(self.n_gpio / self.wordsize)
  51         print("SimpleGPIO: WB Data # of bytes: {0}, #GPIOs: {1}, Rows: {2}"
  52               .format(self.wordsize, self.n_gpio, self.n_rows))
  53         class Spec: pass
  54         spec = Spec()
  55         spec.addr_wid = 30
  56         spec.mask_wid = 4
  57         spec.reg_wid = wordsize*8 # 32
  58         self.bus = Record(make_wb_layout(spec), name="gpio_wb")
  59
  60         #print("CSRBUS layout: ", csrbus_layout)
  61         # MultiCSR read and write buses
  62         temp = []
  63         for i in range(self.wordsize):
  64             temp_str = "rd_word{}".format(i)
  65             temp.append(Record(name=temp_str, layout=csrbus_layout))
  66         self.rd_multicsr = Array(temp)
  67
  68         temp = []
  69         for i in range(self.wordsize):
  70             temp_str = "wr_word{}".format(i)
  71             temp.append(Record(name=temp_str, layout=csrbus_layout))
  72         self.wr_multicsr = Array(temp)
  73
  74         temp = []
  75         for i in range(self.n_gpio):
  76             temp_str = "gpio{}".format(i)
  77             temp.append(Record(name=temp_str, layout=gpio_layout))
  78         self.gpio_ports = Array(temp)
  79
  80     def elaborate(self, platform):
  81         m = Module()
  82         comb, sync = m.d.comb, m.d.sync
  83
  84         bus = self.bus
  85         wb_rd_data = bus.dat_r
  86         wb_wr_data = bus.dat_w
  87         wb_ack = bus.ack
  88
  89         gpio_ports = self.gpio_ports
  90         wr_multi = self.wr_multicsr
  91         rd_multi = self.rd_multicsr
  92
  93         # Flag for indicating rd/wr transactions
  94         new_transaction = Signal(1)
  95
  96         # One address used to configure CSR, set output, read input
  97         with m.If(bus.cyc & bus.stb):
  98             sync += new_transaction.eq(1)
  99
 100             with m.If(bus.we): # write
 101                 sync += wb_ack.eq(1) # always ack, always delayed
 102                 # Split the WB data into bytes for individual GPIOs
 103                 sync += Cat(*wr_multi).eq(wb_wr_data)
 104             with m.Else():
 105                 # Update the read multi bus with current GPIO configs
 106                 # not ack'ing as we need to wait 1 clk cycle before data ready
 107                 # New code based on Luke's idea (still using intermediate
 108                 # signal for Layouts)
 109                 for i in range(len(bus.sel)):
 110                     GPIO_num = Signal(16) # fixed for now
 111                     comb += GPIO_num.eq(bus.adr*len(bus.sel)+i)
 112                     with m.If(bus.sel[i]):
 113                         sync += rd_multi[i].oe.eq(gpio_ports[GPIO_num].oe)
 114                         sync += rd_multi[i].ie.eq(~gpio_ports[GPIO_num].oe)
 115                         sync += rd_multi[i].puen.eq(gpio_ports[GPIO_num].puen)
 116                         sync += rd_multi[i].pden.eq(gpio_ports[GPIO_num].pden)
 117                         with m.If (gpio_ports[GPIO_num].oe):
 118                             sync += rd_multi[i].io.eq(gpio_ports[GPIO_num].o)
 119                         with m.Else():
 120                             sync += rd_multi[i].io.eq(gpio_ports[GPIO_num].i)
 121                         sync += rd_multi[i].bank.eq(gpio_ports[GPIO_num].bank)
 122                     with m.Else():
 123                         sync += rd_multi[i].oe.eq(0)
 124                         sync += rd_multi[i].ie.eq(0)
 125                         sync += rd_multi[i].puen.eq(0)
 126                         sync += rd_multi[i].pden.eq(0)
 127                         sync += rd_multi[i].io.eq(0)
 128                         sync += rd_multi[i].bank.eq(0)
 129         with m.Else():
 130             sync += new_transaction.eq(0)
 131             sync += wb_ack.eq(0)
 132
 133         # Delayed from the start of transaction by 1 clk cycle
 134         with m.If(new_transaction):
 135             # Update the GPIO configs with sent parameters
 136             with m.If(bus.we):
 137                 for i in range(len(bus.sel)):
 138                     GPIO_num = Signal(16) # fixed for now
 139                     comb += GPIO_num.eq(bus.adr*len(bus.sel)+i)
 140                     with m.If(bus.sel[i]):
 141                         sync += gpio_ports[GPIO_num].oe.eq(wr_multi[i].oe)
 142                         sync += gpio_ports[GPIO_num].puen.eq(wr_multi[i].puen)
 143                         sync += gpio_ports[GPIO_num].pden.eq(wr_multi[i].pden)
 144                         with m.If (wr_multi[i].oe):
 145                             sync += gpio_ports[GPIO_num].o.eq(wr_multi[i].io)
 146                         with m.Else():
 147                             sync += gpio_ports[GPIO_num].o.eq(0)
 148                         sync += gpio_ports[GPIO_num].bank.eq(wr_multi[i].bank)
 149                 sync += wb_ack.eq(0) # stop ack'ing!
 150             # Copy the GPIO config data in read multi bus to the WB data bus
 151             # Ack as we're done
 152             with m.Else():
 153                 sync += wb_rd_data.eq(Cat(*rd_multi))
 154                 sync += wb_ack.eq(1) # Delay ack until rd data is ready!
 155         return m
 156
 157     def __iter__(self):
 158         for field in self.bus.fields.values():
 159             yield field
 160         for gpio in range(len(self.gpio_ports)):
 161             for field in self.gpio_ports[gpio].fields.values():
 162                 yield field
 163
 164     def ports(self):
 165         return list(self)
 166
 167 """
 168 def gpio_test_in_pattern(dut, pattern):
 169     num_gpios = len(dut.gpio_ports)
 170     print("Test pattern:")
 171     print(pattern)
 172     for pat in range(0, len(pattern)):
 173         for gpio in range(0, num_gpios):
 174             yield gpio_set_in_pad(dut, gpio, pattern[pat])
 175             yield
 176             temp = yield from gpio_rd_input(dut, gpio)
 177             print("Pattern: {0}, Reading {1}".format(pattern[pat], temp))
 178             assert (temp == pattern[pat])
 179             pat += 1
 180             if pat == len(pattern):
 181                 break
 182 """
 183
 184 def test_gpio_single(dut, gpio, use_random=True):
 185     oe = 1
 186     ie = 0
 187     output = 0
 188     puen = 0
 189     pden = 0
 190     if use_random:
 191         bank = randint(0, (2**NUMBANKBITS)-1)
 192         print("Random bank select: {0:b}".format(bank))
 193     else:
 194         bank = 3 # not special, chose for testing
 195
 196     gpio_csr = yield from gpio_config(dut, gpio, oe, ie, puen, pden, output,
 197                                       bank, check=True)
 198     # Enable output
 199     output = 1
 200     gpio_csr = yield from gpio_config(dut, gpio, oe, ie, puen, pden, output,
 201                                       bank, check=True)
 202
 203 # Shadow reg container class
 204 class GPIOConfigReg():
 205     def __init__(self, shift_dict):
 206         self.shift_dict = shift_dict
 207         self.oe=0
 208         self.ie=0
 209         self.puen=0
 210         self.pden=0
 211         self.io=0
 212         self.bank=0
 213         self.packed=0
 214
 215     def set(self, oe=0, ie=0, puen=0, pden=0, io=0, bank=0):
 216         self.oe=oe
 217         self.ie=ie
 218         self.puen=puen
 219         self.pden=pden
 220         self.io=io
 221         self.bank=bank
 222         self.pack() # Produce packed byte for sending
 223
 224     def set_out(self, outval):
 225         self.io=outval
 226         self.pack() # Produce packed byte for sending
 227
 228     # Take config parameters of specified GPIOs, and combine them to produce
 229     # bytes for sending via WB bus
 230     def pack(self):
 231         self.packed = ((self.oe   << self.shift_dict['oe'])
 232                      | (self.ie   << self.shift_dict['ie'])
 233                      | (self.puen << self.shift_dict['puen'])
 234                      | (self.pden << self.shift_dict['pden'])
 235                      | (self.io   << self.shift_dict['io'])
 236                      | (self.bank << self.shift_dict['bank']))
 237
 238         #print("GPIO Packed CSR: {0:x}".format(self.packed))
 239
 240 # Object for storing each gpio's config state
 241
 242 class GPIOManager():
 243     def __init__(self, dut, layout, wb_bus):
 244         self.dut = dut
 245         self.wb_bus = wb_bus
 246         # arrangement of config bits making up csr word
 247         self.csr_layout = layout
 248         self.shift_dict = self._create_shift_dict()
 249         self.n_gpios = len(self.dut.gpio_ports)
 250         print(dir(self.dut))
 251         # Since GPIO HDL block already has wordsize parameter, use directly
 252         # Alternatively, can derive from WB data r/w buses (div by 8 for bytes)
 253         #self.wordsize = len(self.dut.gpio_wb__dat_w) / 8
 254         self.wordsize = self.dut.wordsize
 255         self.n_rows = ceil(self.n_gpios / self.wordsize)
 256         self.shadow_csr = []
 257         for i in range(self.n_gpios):
 258             self.shadow_csr.append(GPIOConfigReg(self.shift_dict))
 259
 260     def print_info(self):
 261         print("----------")
 262         print("GPIO Block Info:")
 263         print("Number of GPIOs: {}".format(self.n_gpios))
 264         print("WB Data bus width (in bytes): {}".format(self.wordsize))
 265         print("Number of rows: {}".format(self.n_rows))
 266         print("----------")
 267
 268     # The shifting of control bits in the configuration word is dependent on the
 269     # defined layout. To prevent maintaining the shift constants in a separate
 270     # location, the same layout is used to generate a dictionary of bit shifts
 271     # with which the configuration word can be produced!
 272     def _create_shift_dict(self):
 273         shift = 0
 274         shift_dict = {}
 275         for i in range(0, len(self.csr_layout)):
 276             shift_dict[self.csr_layout[i][0]] = shift
 277             shift += self.csr_layout[i][1]
 278         print(shift_dict)
 279         return shift_dict
 280
 281     def _parse_gpio_arg(self, gpio_str):
 282         # TODO: No input checking!
 283         print("Given GPIO/range string: {}".format(gpio_str))
 284         if gpio_str == "all":
 285             start = 0
 286             end = self.n_gpios
 287         elif '-' in gpio_str:
 288             start, end = gpio_str.split('-')
 289             start = int(start)
 290             end = int(end) + 1
 291             if (end < start) or (end > self.n_gpios):
 292                 raise Exception("Second GPIO must be higher than first and"
 293                         + " must be lower or equal to last available GPIO.")
 294         else:
 295             start = int(gpio_str)
 296             if start >= self.n_gpios:
 297                 raise Exception("GPIO must be less/equal to last GPIO.")
 298             end = start + 1
 299         print("Parsed GPIOs {0} until {1}".format(start, end))
 300         return start, end
 301
 302     # Take a combined word and update shadow reg's
 303     # TODO: convert hard-coded sizes to use the csrbus_layout (or dict?)
 304     def update_single_shadow(self, csr_byte, gpio):
 305         oe   = (csr_byte >> self.shift_dict['oe']) & 0x1
 306         ie   = (csr_byte >> self.shift_dict['ie']) & 0x1
 307         puen = (csr_byte >> self.shift_dict['puen']) & 0x1
 308         pden = (csr_byte >> self.shift_dict['pden']) & 0x1
 309         io   = (csr_byte >> self.shift_dict['io']) & 0x1
 310         bank = (csr_byte >> self.shift_dict['bank']) & 0x3
 311
 312         print("csr={0:x} | oe={1}, ie={2}, puen={3}, pden={4}, io={5}, bank={6}"
 313               .format(csr_byte, oe, ie, puen, pden, io, bank))
 314
 315         self.shadow_csr[gpio].set(oe, ie, puen, pden, io, bank)
 316         return oe, ie, puen, pden, io, bank
 317
 318     def rd_csr(self, row_start):
 319         row_word = yield from wb_read(self.wb_bus, row_start)
 320         print("Returned CSR: {0:x}".format(row_word))
 321         return row_word
 322
 323     # Update a single row of configuration registers
 324     def wr_row(self, row_addr, check=False):
 325         curr_gpio = row_addr * self.wordsize
 326         config_word = 0
 327         for byte in range(0, self.wordsize):
 328             if curr_gpio >= self.n_gpios:
 329                 break
 330             config_word += self.shadow_csr[curr_gpio].packed << (8 * byte)
 331             #print("Reading GPIO{} shadow reg".format(curr_gpio))
 332             curr_gpio += 1
 333         print("Writing shadow CSRs val {0:x}  to row addr {1:x}"
 334               .format(config_word, row_addr))
 335         yield from wb_write(self.wb_bus, row_addr, config_word)
 336         yield # Allow one clk cycle to propagate
 337
 338         if(check):
 339             read_word = yield from self.rd_row(row_addr)
 340             assert config_word == read_word
 341
 342     # Read a single address row of GPIO CSRs, and update shadow
 343     def rd_row(self, row_addr):
 344         read_word = yield from self.rd_csr(row_addr)
 345         curr_gpio = row_addr * self.wordsize
 346         single_csr = 0
 347         for byte in range(0, self.wordsize):
 348             if curr_gpio >= self.n_gpios:
 349                 break
 350             single_csr = (read_word >> (8 * byte)) & 0xFF
 351             #print("Updating GPIO{0} shadow reg to {1:x}"
 352             #      .format(curr_gpio, single_csr))
 353             self.update_single_shadow(single_csr, curr_gpio)
 354             curr_gpio += 1
 355         return read_word
 356
 357     # Write all shadow registers to GPIO block
 358     def wr_all(self, check=False):
 359         for row in range(0, self.n_rows):
 360             yield from self.wr_row(row, check)
 361
 362     # Read all GPIO block row addresses and update shadow reg's
 363     def rd_all(self, check=False):
 364         for row in range(0, self.n_rows):
 365             yield from self.rd_row(row, check)
 366
 367     def config(self, gpio_str, oe, ie, puen, pden, outval, bank, check=False):
 368         start, end = self._parse_gpio_arg(gpio_str)
 369         # Update the shadow configuration
 370         for gpio in range(start, end):
 371             # print(oe, ie, puen, pden, outval, bank)
 372             self.shadow_csr[gpio].set(oe, ie, puen, pden, outval, bank)
 373         # TODO: only update the required rows?
 374         yield from self.wr_all()
 375
 376     # Set/Clear the output bit for single or group of GPIOs
 377     def set_out(self, gpio_str, outval):
 378         start, end = self._parse_gpio_arg(gpio_str)
 379         for gpio in range(start, end):
 380             self.shadow_csr[gpio].set_out(outval)
 381
 382         if start == end:
 383             print("Setting GPIO{0} output to {1}".format(start, outval))
 384         else:
 385             print("Setting GPIOs {0}-{1} output to {2}"
 386                   .format(start, end-1, outval))
 387
 388         yield from self.wr_all()
 389
 390     def rd_input(self, gpio_str): # REWORK
 391         start, end = self._parse_gpio_arg(gpio_str)
 392         curr_gpio = 0
 393         # Too difficult to think about, just read all configs
 394         #start_row = floor(start / self.wordsize)
 395         # Hack because end corresponds to range limit, but maybe on same row
 396         # TODO: clean
 397         #end_row = floor( (end-1) / self.wordsize) + 1
 398         read_data = [0] * self.n_rows
 399         for row in range(0, self.n_rows):
 400             read_data[row] = yield from self.rd_row(row)
 401
 402         num_to_read = (end - start)
 403         read_in = [0] * num_to_read
 404         curr_gpio = 0
 405         for i in range(0, num_to_read):
 406             read_in[i] = self.shadow_csr[curr_gpio].io
 407             curr_gpio += 1
 408
 409         print("GPIOs {0} until {1}, i={2}".format(start, end, read_in))
 410         return read_in
 411
 412     # TODO: There's probably a cleaner way to clear the bit...
 413     def sim_set_in_pad(self, gpio_str, in_val):
 414         start, end = self._parse_gpio_arg(gpio_str)
 415         for gpio in range(start, end):
 416             old_in_val = yield self.dut.gpio_ports[gpio].i
 417             print(old_in_val)
 418             print("GPIO{0} Previous i: {1:b} | New i: {2:b}"
 419                   .format(gpio, old_in_val, in_val))
 420             yield self.dut.gpio_ports[gpio].i.eq(in_val)
 421             yield # Allow one clk cycle to propagate
 422
 423     def rd_shadow(self):
 424         shadow_csr = [0] * self.n_gpios
 425         for gpio in range(0, self.n_gpios):
 426             shadow_csr[gpio] = self.shadow_csr[gpio].packed
 427
 428         hex_str = ""
 429         for reg in shadow_csr:
 430             hex_str += " "+hex(reg)
 431         print("Shadow reg's: ", hex_str)
 432
 433         return shadow_csr
 434
 435
 436 def sim_gpio(dut, use_random=True):
 437     #print(dut)
 438     #print(dir(dut.gpio_ports))
 439     #print(len(dut.gpio_ports))
 440
 441     gpios = GPIOManager(dut, csrbus_layout)
 442     gpios.print_info()
 443     # TODO: not working yet
 444     #test_pattern = []
 445     #for i in range(0, (num_gpios * 2)):
 446     #    test_pattern.append(randint(0,1))
 447     #yield from gpio_test_in_pattern(dut, test_pattern)
 448
 449     #yield from gpio_config(dut, start_gpio, oe, ie, puen, pden, outval, bank, end_gpio, check=False, wordsize=4)
 450     #reg_val = 0xC56271A2
 451     #reg_val =  0xFFFFFFFF
 452     #yield from reg_write(dut, 0, reg_val)
 453     #yield from reg_write(dut, 0, reg_val)
 454     #yield
 455
 456     #csr_val = yield from wb_read(dut.bus, 0)
 457     #print("CSR Val: {0:x}".format(csr_val))
 458     print("Finished the simple GPIO block test!")
 459
 460 def gen_gtkw_doc(n_gpios, wordsize, filename):
 461     # GTKWave doc generation
 462     wb_data_width = wordsize*8
 463     n_rows = ceil(n_gpios/wordsize)
 464     style = {
 465         '': {'base': 'hex'},
 466         'in': {'color': 'orange'},
 467         'out': {'color': 'yellow'},
 468         'debug': {'module': 'top', 'color': 'red'}
 469     }
 470
 471     # Create a trace list, each block expected to be a tuple()
 472     traces = []
 473     wb_traces = ('Wishbone Bus', [
 474                         ('gpio_wb__cyc', 'in'),
 475                         ('gpio_wb__stb', 'in'),
 476                         ('gpio_wb__we', 'in'),
 477                         ('gpio_wb__adr[27:0]', 'in'),
 478                         ('gpio_wb__sel[3:0]', 'in'),
 479                         ('gpio_wb__dat_w[{}:0]'.format(wb_data_width-1), 'in'),
 480                         ('gpio_wb__dat_r[{}:0]'.format(wb_data_width-1), 'out'),
 481                         ('gpio_wb__ack', 'out'),
 482                 ])
 483     traces.append(wb_traces)
 484
 485     gpio_internal_traces = ('Internal', [
 486                                 ('clk', 'in'),
 487                                 ('new_transaction'),
 488                                 ('rst', 'in')
 489                             ])
 490     traces.append(gpio_internal_traces)
 491
 492     traces.append({'comment': 'Multi-byte GPIO config read bus'})
 493     for word in range(0, wordsize):
 494         prefix = "rd_word{}__".format(word)
 495         single_word = []
 496         word_signals = []
 497         single_word.append('Word{}'.format(word))
 498         word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1)))
 499         word_signals.append((prefix+'ie'))
 500         word_signals.append((prefix+'io'))
 501         word_signals.append((prefix+'oe'))
 502         word_signals.append((prefix+'pden'))
 503         word_signals.append((prefix+'puen'))
 504         single_word.append(word_signals)
 505         traces.append(tuple(single_word))
 506
 507     traces.append({'comment': 'Multi-byte GPIO config write bus'})
 508     for word in range(0, wordsize):
 509         prefix = "wr_word{}__".format(word)
 510         single_word = []
 511         word_signals = []
 512         single_word.append('Word{}'.format(word))
 513         word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1)))
 514         word_signals.append((prefix+'ie'))
 515         word_signals.append((prefix+'io'))
 516         word_signals.append((prefix+'oe'))
 517         word_signals.append((prefix+'pden'))
 518         word_signals.append((prefix+'puen'))
 519         single_word.append(word_signals)
 520         traces.append(tuple(single_word))
 521
 522     for gpio in range(0, n_gpios):
 523         prefix = "gpio{}__".format(gpio)
 524         single_gpio = []
 525         gpio_signals = []
 526         single_gpio.append('GPIO{} Port'.format(gpio))
 527         gpio_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1), 'out'))
 528         gpio_signals.append( (prefix+'i', 'in') )
 529         gpio_signals.append( (prefix+'o', 'out') )
 530         gpio_signals.append( (prefix+'oe', 'out') )
 531         gpio_signals.append( (prefix+'pden', 'out') )
 532         gpio_signals.append( (prefix+'puen', 'out') )
 533         single_gpio.append(gpio_signals)
 534         traces.append(tuple(single_gpio))
 535
 536     #print(traces)
 537
 538     #module = "top.xics_icp"
 539     module = "bench.top.xics_icp"
 540     write_gtkw(filename+".gtkw", filename+".vcd", traces, style,
 541                module=module)
 542
 543 def test_gpio():
 544     filename = "test_gpio" # Doesn't include extension
 545     n_gpios = 8
 546     wordsize = 4 # Number of bytes in the WB data word
 547     dut = SimpleGPIO(wordsize, n_gpios)
 548     vl = rtlil.convert(dut, ports=dut.ports())
 549     with open(filename+".il", "w") as f:
 550         f.write(vl)
 551
 552     m = Module()
 553     m.submodules.xics_icp = dut
 554
 555     sim = Simulator(m)
 556     sim.add_clock(1e-6)
 557
 558     #sim.add_sync_process(wrap(sim_gpio(dut, use_random=False)))
 559     sim.add_sync_process(wrap(test_gpioman(dut)))
 560     sim_writer = sim.write_vcd(filename+".vcd")
 561     with sim_writer:
 562         sim.run()
 563
 564     gen_gtkw_doc(n_gpios, wordsize, filename)
 565
 566 def test_gpioman(dut):
 567     print("------START----------------------")
 568     gpios = GPIOManager(dut, csrbus_layout, dut.bus)
 569     gpios.print_info()
 570     #gpios._parse_gpio_arg("all")
 571     #gpios._parse_gpio_arg("0")
 572     #gpios._parse_gpio_arg("1-3")
 573     #gpios._parse_gpio_arg("20")
 574
 575     oe = 1
 576     ie = 0
 577     puen = 0
 578     pden = 1
 579     outval = 0
 580     bank = 3
 581     yield from gpios.config("0-3", oe=1, ie=0, puen=0, pden=1, outval=0, bank=2)
 582     ie = 1
 583     yield from gpios.config("4-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=6)
 584     yield from gpios.set_out("0-1", outval=1)
 585
 586     #yield from gpios.rd_all()
 587     yield from gpios.sim_set_in_pad("6-7", 1)
 588     print("----------------------------")
 589     yield from gpios.rd_input("4-7")
 590
 591     gpios.rd_shadow()
 592
 593 if __name__ == '__main__':
 594     test_gpio()
 595