src/spec/simple_gpio.py

   1 """Simple GPIO peripheral on wishbone
   2
   3 This is an extremely simple GPIO peripheral intended for use in XICS
   4 testing, however it could also be used as an actual GPIO peripheral
   5
   6 Modified for use with pinmux, will probably change the class name later.
   7 """
   8 from random import randint
   9 from math import ceil, floor
  10 from nmigen import Elaboratable, Module, Signal, Record, Array, Cat, Const
  11 from nmigen.hdl.rec import Layout
  12 from nmigen.utils import log2_int
  13 from nmigen.cli import rtlil
  14 from soc.minerva.wishbone import make_wb_layout
  15 from nmutil.util import wrap
  16 from soc.bus.test.wb_rw import wb_read, wb_write
  17
  18 from nmutil.gtkw import write_gtkw
  19
  20 cxxsim = False
  21 if cxxsim:
  22     from nmigen.sim.cxxsim import Simulator, Settle
  23 else:
  24     from nmigen.sim import Simulator, Settle
  25
  26 # Layout of 8-bit configuration word:
  27 # bank[2:0] i/o | pden puen ien oe
  28 NUMBANKBITS = 3 # max 3 bits, only supporting 4 banks (0-3)
  29 csrbus_layout = (("oe", 1),
  30                  ("ie", 1),
  31                  ("puen", 1),
  32                  ("pden", 1),
  33                  ("io", 1),
  34                  ("bank", NUMBANKBITS)
  35                 )
  36
  37 gpio_layout = (("i", 1),
  38                ("oe", 1),
  39                ("o", 1),
  40                ("puen", 1),
  41                ("pden", 1),
  42                ("bank", NUMBANKBITS)
  43               )
  44
  45 class SimpleGPIO(Elaboratable):
  46
  47     def __init__(self, wordsize=4, n_gpio=16):
  48         self.wordsize = wordsize
  49         self.n_gpio = n_gpio
  50         self.n_rows = ceil(self.n_gpio / self.wordsize)
  51         print("SimpleGPIO: WB Data # of bytes: {0}, #GPIOs: {1}, Rows: {2}"
  52               .format(self.wordsize, self.n_gpio, self.n_rows))
  53         class Spec: pass
  54         spec = Spec()
  55         spec.addr_wid = 30
  56         spec.mask_wid = 4
  57         spec.reg_wid = wordsize*8 # 32
  58         self.bus = Record(make_wb_layout(spec), name="gpio_wb")
  59
  60         #print("CSRBUS layout: ", csrbus_layout)
  61         # MultiCSR read and write buses
  62         temp = []
  63         for i in range(self.wordsize):
  64             temp_str = "rd_word{}".format(i)
  65             temp.append(Record(name=temp_str, layout=csrbus_layout))
  66         self.rd_multicsr = Array(temp)
  67
  68         temp = []
  69         for i in range(self.wordsize):
  70             temp_str = "word{}".format(i)
  71             temp.append(Record(name=temp_str, layout=csrbus_layout))
  72         self.multicsrbus = Array(temp)
  73
  74         temp = []
  75         for i in range(self.n_gpio):
  76             temp_str = "gpio{}".format(i)
  77             temp.append(Record(name=temp_str, layout=gpio_layout))
  78         self.gpio_ports = Array(temp)
  79
  80     def elaborate(self, platform):
  81         m = Module()
  82         comb, sync = m.d.comb, m.d.sync
  83
  84         bus = self.bus
  85         wb_rd_data = bus.dat_r
  86         wb_wr_data = bus.dat_w
  87         wb_rd_data_reg = Signal(self.wordsize*8) # same len as WB bus
  88         wb_ack = bus.ack
  89
  90         gpio_ports = self.gpio_ports
  91         multi = self.multicsrbus
  92         rd_multi = self.rd_multicsr
  93
  94         # Flag for indicating rd/wr transactions
  95         new_transaction = Signal(1)
  96
  97         #print("Types:")
  98         #print("gpio_addr: ", type(gpio_addr))
  99
 100         # One address used to configure CSR, set output, read input
 101         with m.If(bus.cyc & bus.stb):
 102             sync += wb_ack.eq(1) # always ack, always delayed
 103             # TODO: is this needed anymore?
 104             sync += new_transaction.eq(1)
 105             # Concatinate the GPIO configs that are on the same "row" or
 106             # address and send
 107             multi_cat = []
 108             for i in range(0, self.wordsize):
 109                 multi_cat.append(rd_multi[i])
 110             sync += wb_rd_data_reg.eq(Cat(multi_cat))
 111             with m.If(bus.we): # write
 112                 # Configure CSR
 113                 for byte in range(0, self.wordsize):
 114                     # TODO: wasteful... convert to Cat(), somehow
 115                     sync += multi[byte].eq(wb_wr_data[byte*8:8+byte*8])
 116             with m.Elif(wb_ack): # read (and acked)
 117                 comb += wb_rd_data.eq(wb_rd_data_reg)
 118         with m.Else():
 119             sync += new_transaction.eq(0)
 120             sync += wb_ack.eq(0)
 121
 122         # Only update GPIOs config if a new transaction happened last cycle
 123         # (read or write). Always lags from multi csrbus by 1 clk cycle, most
 124         # sane way I could think of while using Record().
 125         with m.If(new_transaction):
 126             self.connect_wr_bus_to_gpio(m, sync, bus.adr, gpio_ports, multi)
 127         self.connect_gpio_to_rd_bus(m, sync, bus.adr, gpio_ports, rd_multi)
 128         #with m.Else():
 129         #    print("Copy gpio_ports to multi...")
 130         #    sync += multi[]
 131         return m
 132
 133     def connect_wr_bus_to_gpio(self, module, domain, addr, gp, multi):
 134         if self.n_gpio > self.wordsize:
 135             print("#GPIOs is greater than, and is a multiple of WB wordsize")
 136             # Case where all gpios fit within full words
 137             if self.n_gpio % self.wordsize == 0:
 138                 for row in range(self.n_rows):
 139                     with module.If(addr == Const(row)):
 140                         offset = row*self.wordsize
 141                         for byte in range(self.wordsize):
 142                             domain += gp[byte+offset].oe.eq(multi[byte].oe)
 143                             domain += gp[byte+offset].puen.eq(multi[byte].puen)
 144                             domain += gp[byte+offset].pden.eq(multi[byte].pden)
 145                             # prevent output being set if GPIO configured as i
 146                             # TODO: No checking is done if ie/oe high together
 147                             with module.If(multi[byte].oe):
 148                                 domain += gp[byte+offset].o.eq(multi[byte].io)
 149                             with module.Else():
 150                                 domain += multi[byte].io.eq(gp[byte+offset].i)
 151                             domain += gp[byte+offset].bank.eq(multi[byte].bank)
 152             else:
 153                 # TODO: This is a complex case, not needed atm
 154                 print("#GPIOs is greater than WB wordsize")
 155                 print("But not fully fitting in words...")
 156                 print("NOT IMPLEMENTED THIS CASE")
 157                 raise
 158         else:
 159             print("#GPIOs is less or equal to WB wordsize (in bytes)")
 160             for byte in range(self.n_gpio):
 161                 domain += gp[byte].oe.eq(multi[byte].oe)
 162                 domain += gp[byte].puen.eq(multi[byte].puen)
 163                 domain += gp[byte].pden.eq(multi[byte].pden)
 164                 # Check to prevent output being set if GPIO configured as i
 165                 # TODO: No checking is done if ie/oe high together
 166                 with module.If(multi[byte].oe):
 167                     domain += gp[byte].o.eq(multi[byte].io)
 168                 with module.Else():
 169                     domain += gp[byte].o.eq(0)
 170                 domain += gp[byte].bank.eq(multi[byte].bank)
 171
 172     def connect_gpio_to_rd_bus(self, module, domain, addr, gp, multi):
 173         if self.n_gpio > self.wordsize:
 174             print("#GPIOs is greater than, and is a multiple of WB wordsize")
 175             # Case where all gpios fit within full words
 176             if self.n_gpio % self.wordsize == 0:
 177                 for row in range(self.n_rows):
 178                     with module.If(addr == Const(row)):
 179                         offset = row*self.wordsize
 180                         for byte in range(self.wordsize):
 181                             domain += multi[byte].oe.eq(gp[byte+offset].oe)
 182                             domain += multi[byte].puen.eq(gp[byte+offset].puen)
 183                             domain += multi[byte].pden.eq(gp[byte+offset].pden)
 184                             # prevent output being set if GPIO configured as i
 185                             # TODO: No checking is done if ie/oe high together
 186                             with module.If(gp[byte+offset].oe):
 187                                 domain += multi[byte].io.eq(gp[byte+offset].o)
 188                             with module.Else():
 189                                 domain += multi[byte].io.eq(gp[byte+offset].i)
 190                             domain += multi[byte].bank.eq(gp[byte+offset].bank)
 191             else:
 192                 # TODO: This is a complex case, not needed atm
 193                 print("#GPIOs is greater than WB wordsize")
 194                 print("NOT IMPLEMENTED THIS CASE")
 195                 raise
 196         else:
 197             print("#GPIOs is less or equal to WB wordsize (in bytes)")
 198             for byte in range(self.n_gpio):
 199                 domain += multi[byte].oe.eq(gp[gpio].oe)
 200                 domain += multi[byte].puen.eq(gp[gpio].puen)
 201                 domain += multi[byte].pden.eq(gp[gpio].pden)
 202                 # Check to prevent output being set if GPIO configured as i
 203                 # TODO: No checking is done if ie/oe high together
 204                 with module.If(multi[byte].oe):
 205                     domain += multi[byte].io.eq(gp[gpio].o)
 206                 with module.Else():
 207                     domain += multi[byte].io.eq(gp[byte].i)
 208                 domain += multi[byte].bank.eq(gp[gpio].bank)
 209
 210
 211     def __iter__(self):
 212         for field in self.bus.fields.values():
 213             yield field
 214         for gpio in range(len(self.gpio_ports)):
 215             for field in self.gpio_ports[gpio].fields.values():
 216                 yield field
 217
 218     def ports(self):
 219         return list(self)
 220
 221 """
 222 def gpio_test_in_pattern(dut, pattern):
 223     num_gpios = len(dut.gpio_ports)
 224     print("Test pattern:")
 225     print(pattern)
 226     for pat in range(0, len(pattern)):
 227         for gpio in range(0, num_gpios):
 228             yield gpio_set_in_pad(dut, gpio, pattern[pat])
 229             yield
 230             temp = yield from gpio_rd_input(dut, gpio)
 231             print("Pattern: {0}, Reading {1}".format(pattern[pat], temp))
 232             assert (temp == pattern[pat])
 233             pat += 1
 234             if pat == len(pattern):
 235                 break
 236 """
 237
 238 def test_gpio_single(dut, gpio, use_random=True):
 239     oe = 1
 240     ie = 0
 241     output = 0
 242     puen = 0
 243     pden = 0
 244     if use_random:
 245         bank = randint(0, (2**NUMBANKBITS)-1)
 246         print("Random bank select: {0:b}".format(bank))
 247     else:
 248         bank = 3 # not special, chose for testing
 249
 250     gpio_csr = yield from gpio_config(dut, gpio, oe, ie, puen, pden, output,
 251                                       bank, check=True)
 252     # Enable output
 253     output = 1
 254     gpio_csr = yield from gpio_config(dut, gpio, oe, ie, puen, pden, output,
 255                                       bank, check=True)
 256
 257 # Shadow reg container class
 258 class GPIOConfigReg():
 259     def __init__(self, shift_dict):
 260         self.shift_dict = shift_dict
 261         self.oe=0
 262         self.ie=0
 263         self.puen=0
 264         self.pden=0
 265         self.io=0
 266         self.bank=0
 267         self.packed=0
 268
 269     def set(self, oe=0, ie=0, puen=0, pden=0, io=0, bank=0):
 270         self.oe=oe
 271         self.ie=ie
 272         self.puen=puen
 273         self.pden=pden
 274         self.io=io
 275         self.bank=bank
 276         self.pack() # Produce packed byte for sending
 277
 278     def set_out(self, outval):
 279         self.io=outval
 280         self.pack() # Produce packed byte for sending
 281
 282     # Take config parameters of specified GPIOs, and combine them to produce
 283     # bytes for sending via WB bus
 284     def pack(self):
 285         self.packed = ((self.oe   << self.shift_dict['oe'])
 286                      | (self.ie   << self.shift_dict['ie'])
 287                      | (self.puen << self.shift_dict['puen'])
 288                      | (self.pden << self.shift_dict['pden'])
 289                      | (self.io   << self.shift_dict['io'])
 290                      | (self.bank << self.shift_dict['bank']))
 291
 292         #print("GPIO Packed CSR: {0:x}".format(self.packed))
 293
 294 # Object for storing each gpio's config state
 295
 296 class GPIOManager():
 297     def __init__(self, dut, layout, wb_bus):
 298         self.dut = dut
 299         self.wb_bus = wb_bus
 300         # arrangement of config bits making up csr word
 301         self.csr_layout = layout
 302         self.shift_dict = self._create_shift_dict()
 303         self.n_gpios = len(self.dut.gpio_ports)
 304         print(dir(self.dut))
 305         # Since GPIO HDL block already has wordsize parameter, use directly
 306         # Alternatively, can derive from WB data r/w buses (div by 8 for bytes)
 307         #self.wordsize = len(self.dut.gpio_wb__dat_w) / 8
 308         self.wordsize = self.dut.wordsize
 309         self.n_rows = ceil(self.n_gpios / self.wordsize)
 310         self.shadow_csr = []
 311         for i in range(self.n_gpios):
 312             self.shadow_csr.append(GPIOConfigReg(self.shift_dict))
 313
 314     def print_info(self):
 315         print("----------")
 316         print("GPIO Block Info:")
 317         print("Number of GPIOs: {}".format(self.n_gpios))
 318         print("WB Data bus width (in bytes): {}".format(self.wordsize))
 319         print("Number of rows: {}".format(self.n_rows))
 320         print("----------")
 321
 322     # The shifting of control bits in the configuration word is dependent on the
 323     # defined layout. To prevent maintaining the shift constants in a separate
 324     # location, the same layout is used to generate a dictionary of bit shifts
 325     # with which the configuration word can be produced!
 326     def _create_shift_dict(self):
 327         shift = 0
 328         shift_dict = {}
 329         for i in range(0, len(self.csr_layout)):
 330             shift_dict[self.csr_layout[i][0]] = shift
 331             shift += self.csr_layout[i][1]
 332         print(shift_dict)
 333         return shift_dict
 334
 335     def _parse_gpio_arg(self, gpio_str):
 336         # TODO: No input checking!
 337         print("Given GPIO/range string: {}".format(gpio_str))
 338         if gpio_str == "all":
 339             start = 0
 340             end = self.n_gpios
 341         elif '-' in gpio_str:
 342             start, end = gpio_str.split('-')
 343             start = int(start)
 344             end = int(end) + 1
 345             if (end < start) or (end > self.n_gpios):
 346                 raise Exception("Second GPIO must be higher than first and"
 347                         + " must be lower or equal to last available GPIO.")
 348         else:
 349             start = int(gpio_str)
 350             if start >= self.n_gpios:
 351                 raise Exception("GPIO must be less/equal to last GPIO.")
 352             end = start + 1
 353         print("Parsed GPIOs {0} until {1}".format(start, end))
 354         return start, end
 355
 356     # Take a combined word and update shadow reg's
 357     # TODO: convert hard-coded sizes to use the csrbus_layout (or dict?)
 358     def update_single_shadow(self, csr_byte, gpio):
 359         oe   = (csr_byte >> self.shift_dict['oe']) & 0x1
 360         ie   = (csr_byte >> self.shift_dict['ie']) & 0x1
 361         puen = (csr_byte >> self.shift_dict['puen']) & 0x1
 362         pden = (csr_byte >> self.shift_dict['pden']) & 0x1
 363         io   = (csr_byte >> self.shift_dict['io']) & 0x1
 364         bank = (csr_byte >> self.shift_dict['bank']) & 0x3
 365
 366         print("csr={0:x} | oe={1}, ie={2}, puen={3}, pden={4}, io={5}, bank={6}"
 367               .format(csr_byte, oe, ie, puen, pden, io, bank))
 368
 369         self.shadow_csr[gpio].set(oe, ie, puen, pden, io, bank)
 370         return oe, ie, puen, pden, io, bank
 371
 372     def rd_csr(self, row_start):
 373         row_word = yield from wb_read(self.wb_bus, row_start)
 374         print("Returned CSR: {0:x}".format(row_word))
 375         return row_word
 376
 377     # Update a single row of configuration registers
 378     def wr_row(self, row_addr, check=False):
 379         curr_gpio = row_addr * self.wordsize
 380         config_word = 0
 381         for byte in range(0, self.wordsize):
 382             if curr_gpio >= self.n_gpios:
 383                 break
 384             config_word += self.shadow_csr[curr_gpio].packed << (8 * byte)
 385             #print("Reading GPIO{} shadow reg".format(curr_gpio))
 386             curr_gpio += 1
 387         print("Writing shadow CSRs val {0:x}  to row addr {1:x}"
 388               .format(config_word, row_addr))
 389         yield from wb_write(self.wb_bus, row_addr, config_word)
 390         yield # Allow one clk cycle to propagate
 391
 392         if(check):
 393             read_word = yield from self.rd_row(row_addr)
 394             assert config_word == read_word
 395
 396     # Read a single address row of GPIO CSRs, and update shadow
 397     def rd_row(self, row_addr):
 398         read_word = yield from self.rd_csr(row_addr)
 399         curr_gpio = row_addr * self.wordsize
 400         single_csr = 0
 401         for byte in range(0, self.wordsize):
 402             if curr_gpio >= self.n_gpios:
 403                 break
 404             single_csr = (read_word >> (8 * byte)) & 0xFF
 405             #print("Updating GPIO{0} shadow reg to {1:x}"
 406             #      .format(curr_gpio, single_csr))
 407             self.update_single_shadow(single_csr, curr_gpio)
 408             curr_gpio += 1
 409         return read_word
 410
 411     # Write all shadow registers to GPIO block
 412     def wr_all(self, check=False):
 413         for row in range(0, self.n_rows):
 414             yield from self.wr_row(row, check)
 415
 416     # Read all GPIO block row addresses and update shadow reg's
 417     def rd_all(self, check=False):
 418         for row in range(0, self.n_rows):
 419             yield from self.rd_row(row, check)
 420
 421     def config(self, gpio_str, oe, ie, puen, pden, outval, bank, check=False):
 422         start, end = self._parse_gpio_arg(gpio_str)
 423         # Update the shadow configuration
 424         for gpio in range(start, end):
 425             # print(oe, ie, puen, pden, outval, bank)
 426             self.shadow_csr[gpio].set(oe, ie, puen, pden, outval, bank)
 427         # TODO: only update the required rows?
 428         yield from self.wr_all()
 429
 430     # Set/Clear the output bit for single or group of GPIOs
 431     def set_out(self, gpio_str, outval):
 432         start, end = self._parse_gpio_arg(gpio_str)
 433         for gpio in range(start, end):
 434             self.shadow_csr[gpio].set_out(outval)
 435
 436         if start == end:
 437             print("Setting GPIO{0} output to {1}".format(start, outval))
 438         else:
 439             print("Setting GPIOs {0}-{1} output to {2}"
 440                   .format(start, end-1, outval))
 441
 442         yield from self.wr_all()
 443
 444     def rd_input(self, gpio_str): # REWORK
 445         start, end = self._parse_gpio_arg(gpio_str)
 446         curr_gpio = 0
 447         # Too difficult to think about, just read all configs
 448         #start_row = floor(start / self.wordsize)
 449         # Hack because end corresponds to range limit, but maybe on same row
 450         # TODO: clean
 451         #end_row = floor( (end-1) / self.wordsize) + 1
 452         read_data = [0] * self.n_rows
 453         for row in range(0, self.n_rows):
 454             read_data[row] = yield from self.rd_row(row)
 455
 456         num_to_read = (end - start)
 457         read_in = [0] * num_to_read
 458         curr_gpio = 0
 459         for i in range(0, num_to_read):
 460             read_in[i] = self.shadow_csr[curr_gpio].io
 461             curr_gpio += 1
 462
 463         print("GPIOs {0} until {1}, i={2}".format(start, end, read_in))
 464         return read_in
 465
 466     # TODO: There's probably a cleaner way to clear the bit...
 467     def sim_set_in_pad(self, gpio_str, in_val):
 468         start, end = self._parse_gpio_arg(gpio_str)
 469         for gpio in range(start, end):
 470             old_in_val = yield self.dut.gpio_ports[gpio].i
 471             print(old_in_val)
 472             print("GPIO{0} Previous i: {1:b} | New i: {2:b}"
 473                   .format(gpio, old_in_val, in_val))
 474             yield self.dut.gpio_ports[gpio].i.eq(in_val)
 475             yield # Allow one clk cycle to propagate
 476
 477     def rd_shadow(self):
 478         shadow_csr = [0] * self.n_gpios
 479         for gpio in range(0, self.n_gpios):
 480             shadow_csr[gpio] = self.shadow_csr[gpio].packed
 481
 482         hex_str = ""
 483         for reg in shadow_csr:
 484             hex_str += " "+hex(reg)
 485         print("Shadow reg's: ", hex_str)
 486
 487         return shadow_csr
 488
 489
 490 def sim_gpio(dut, use_random=True):
 491     #print(dut)
 492     #print(dir(dut.gpio_ports))
 493     #print(len(dut.gpio_ports))
 494
 495     gpios = GPIOManager(dut, csrbus_layout)
 496     gpios.print_info()
 497     # TODO: not working yet
 498     #test_pattern = []
 499     #for i in range(0, (num_gpios * 2)):
 500     #    test_pattern.append(randint(0,1))
 501     #yield from gpio_test_in_pattern(dut, test_pattern)
 502
 503     #yield from gpio_config(dut, start_gpio, oe, ie, puen, pden, outval, bank, end_gpio, check=False, wordsize=4)
 504     #reg_val = 0xC56271A2
 505     #reg_val =  0xFFFFFFFF
 506     #yield from reg_write(dut, 0, reg_val)
 507     #yield from reg_write(dut, 0, reg_val)
 508     #yield
 509
 510     #csr_val = yield from wb_read(dut.bus, 0)
 511     #print("CSR Val: {0:x}".format(csr_val))
 512     print("Finished the simple GPIO block test!")
 513
 514 def gen_gtkw_doc(n_gpios, wordsize, filename):
 515     # GTKWave doc generation
 516     wb_data_width = wordsize*8
 517     n_rows = ceil(n_gpios/wordsize)
 518     style = {
 519         '': {'base': 'hex'},
 520         'in': {'color': 'orange'},
 521         'out': {'color': 'yellow'},
 522         'debug': {'module': 'top', 'color': 'red'}
 523     }
 524
 525     # Create a trace list, each block expected to be a tuple()
 526     traces = []
 527     wb_traces = ('Wishbone Bus', [
 528                         ('gpio_wb__cyc', 'in'),
 529                         ('gpio_wb__stb', 'in'),
 530                         ('gpio_wb__we', 'in'),
 531                         ('gpio_wb__adr[27:0]', 'in'),
 532                         ('gpio_wb__dat_w[{}:0]'.format(wb_data_width-1), 'in'),
 533                         ('gpio_wb__dat_r[{}:0]'.format(wb_data_width-1), 'out'),
 534                         ('gpio_wb__ack', 'out'),
 535                 ])
 536     traces.append(wb_traces)
 537
 538     gpio_internal_traces = ('Internal', [
 539                                 ('clk', 'in'),
 540                                 ('new_transaction'),
 541                                 ('rst', 'in')
 542                             ])
 543     traces.append(gpio_internal_traces)
 544
 545     traces.append({'comment': 'Multi-byte GPIO config bus'})
 546     for word in range(0, wordsize):
 547         prefix = "word{}__".format(word)
 548         single_word = []
 549         word_signals = []
 550         single_word.append('Word{}'.format(word))
 551         word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1)))
 552         word_signals.append((prefix+'ie'))
 553         word_signals.append((prefix+'io'))
 554         word_signals.append((prefix+'oe'))
 555         word_signals.append((prefix+'pden'))
 556         word_signals.append((prefix+'puen'))
 557         single_word.append(word_signals)
 558         traces.append(tuple(single_word))
 559
 560     for gpio in range(0, n_gpios):
 561         prefix = "gpio{}__".format(gpio)
 562         single_gpio = []
 563         gpio_signals = []
 564         single_gpio.append('GPIO{} Port'.format(gpio))
 565         gpio_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1), 'out'))
 566         gpio_signals.append( (prefix+'i', 'in') )
 567         gpio_signals.append( (prefix+'o', 'out') )
 568         gpio_signals.append( (prefix+'oe', 'out') )
 569         gpio_signals.append( (prefix+'pden', 'out') )
 570         gpio_signals.append( (prefix+'puen', 'out') )
 571         single_gpio.append(gpio_signals)
 572         traces.append(tuple(single_gpio))
 573
 574     #print(traces)
 575
 576     write_gtkw(filename+".gtkw", filename+".vcd", traces, style,
 577                module="top.xics_icp")
 578
 579 def test_gpio():
 580     filename = "test_gpio" # Doesn't include extension
 581     n_gpios = 8
 582     wordsize = 4 # Number of bytes in the WB data word
 583     dut = SimpleGPIO(wordsize, n_gpios)
 584     vl = rtlil.convert(dut, ports=dut.ports())
 585     with open(filename+".il", "w") as f:
 586         f.write(vl)
 587
 588     m = Module()
 589     m.submodules.xics_icp = dut
 590
 591     sim = Simulator(m)
 592     sim.add_clock(1e-6)
 593
 594     #sim.add_sync_process(wrap(sim_gpio(dut, use_random=False)))
 595     sim.add_sync_process(wrap(test_gpioman(dut)))
 596     sim_writer = sim.write_vcd(filename+".vcd")
 597     with sim_writer:
 598         sim.run()
 599
 600     gen_gtkw_doc(n_gpios, wordsize, filename)
 601
 602 def test_gpioman(dut):
 603     print("------START----------------------")
 604     gpios = GPIOManager(dut, csrbus_layout, dut.bus)
 605     gpios.print_info()
 606     #gpios._parse_gpio_arg("all")
 607     #gpios._parse_gpio_arg("0")
 608     #gpios._parse_gpio_arg("1-3")
 609     #gpios._parse_gpio_arg("20")
 610
 611     oe = 1
 612     ie = 0
 613     puen = 0
 614     pden = 1
 615     outval = 0
 616     bank = 3
 617     yield from gpios.config("0-3", oe=1, ie=0, puen=0, pden=1, outval=0, bank=2)
 618     ie = 1
 619     yield from gpios.config("4-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=6)
 620     yield from gpios.set_out("0-3", outval=1)
 621
 622     #yield from gpios.rd_all()
 623     yield from gpios.sim_set_in_pad("4-7", 1)
 624     print("----------------------------")
 625     yield from gpios.rd_input("4-7")
 626
 627     gpios.rd_shadow()
 628
 629 if __name__ == '__main__':
 630     test_gpio()
 631