src/spec/testing.py

   1 from UserDict import UserDict
   2
   3 class Wire(object):
   4     """ a wire which can be hi, lo or tri-state
   5     """
   6     def __init__(self, wires, name):
   7         self.wires = wires
   8         self.wires[name] = self
   9         self.name = name
  10         self.val = 'x'
  11
  12 class TestPin(object):
  13     """ a test pin can be an output, input or in-out
  14         and it stores the state in an associated wire
  15     """
  16
  17 class Wires(UserDict):
  18     """ a set of wires
  19     """
  20     def __init__(self):
  21         UserDict.__init__(self)
  22
  23 def dummytest(ps, output_dir, output_type):
  24     print ps, output_dir, output_type
  25     print dir(ps)
  26     print ps.fnspec
  27
  28     # basically we need to replicate the entirety of the
  29     # verilog module's inputs and outputs, so that we can
  30     # set inputs hi/lo and then test expected outputs hi/lo.
  31     # so, set up some wires by going through the interfaces
  32     w = Wires()