src/test_bsv/pinmux.bsv

   1
   2 /*
   3    This BSV file has been generated by the PinMux tool available at:
   4    https://bitbucket.org/casl/pinmux.
   5
   6    Authors: Neel Gala, Luke
   7    Date of generation: Sun Jul 22 05:31:10 2018
   8 */
   9
  10 package pinmux;
  11
  12    interface MuxSelectionLines;
  13
  14       // declare the method which will capture the user pin-mux
  15       // selection values.The width of the input is dependent on the number
  16       // of muxes happening per IO. For now we have a generalized width
  17       // where each IO will have the same number of muxes.
  18      method  Action cell0_mux (Bit#(2) in);
  19      method  Action cell1_mux (Bit#(2) in);
  20      method  Action cell2_mux (Bit#(2) in);
  21       endinterface
  22
  23
  24       interface IOCellSide;
  25       // declare the interface to the IO cells.
  26       // Each IO cell will have 1 input field (output from pin mux)
  27       // and an output and out-enable field (input to pinmux)
  28           // interface declaration between IO-0 and pinmux
  29     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_out;
  30     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_outen;
  31     (*always_ready,always_enabled,result="io"*) method
  32                        Action io0_cell_in (Bit#(1) in);
  33           // interface declaration between IO-1 and pinmux
  34     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_out;
  35     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_outen;
  36     (*always_ready,always_enabled,result="io"*) method
  37                        Action io1_cell_in (Bit#(1) in);
  38           // interface declaration between IO-2 and pinmux
  39     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_out;
  40     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_outen;
  41     (*always_ready,always_enabled,result="io"*) method
  42                        Action io2_cell_in (Bit#(1) in);
  43       endinterface
  44
  45
  46       interface PeripheralSide;
  47       // declare the interface to the peripherals
  48       // Each peripheral's function will be either an input, output
  49       // or be bi-directional.  an input field will be an output from the
  50       // peripheral and an output field will be an input to the peripheral.
  51       // Bi-directional functions also have an output-enable (which
  52       // again comes *in* from the peripheral)
  53           // interface declaration between UART-0 and pinmux
  54     (*always_ready,always_enabled*) method  Action uart_tx (Bit#(1) in);
  55     (*always_ready,always_enabled*) method  Bit#(1) uart_rx;
  56           // interface declaration between GPIOA-0 and pinmux
  57     (*always_ready,always_enabled*) method  Action gpioa_a0_out (Bit#(1) in);
  58     (*always_ready,always_enabled*) method  Action gpioa_a0_outen (Bit#(1) in);
  59     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a0_in;
  60     (*always_ready,always_enabled*) method  Action gpioa_a1_out (Bit#(1) in);
  61     (*always_ready,always_enabled*) method  Action gpioa_a1_outen (Bit#(1) in);
  62     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a1_in;
  63     (*always_ready,always_enabled*) method  Action gpioa_a2_out (Bit#(1) in);
  64     (*always_ready,always_enabled*) method  Action gpioa_a2_outen (Bit#(1) in);
  65     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a2_in;
  66           // interface declaration between TWI-0 and pinmux
  67     (*always_ready,always_enabled*) method  Action twi_sda_out (Bit#(1) in);
  68     (*always_ready,always_enabled*) method  Action twi_sda_outen (Bit#(1) in);
  69     (*always_ready,always_enabled*) method  Bit#(1) twi_sda_in;
  70     (*always_ready,always_enabled*) method  Action twi_scl_out (Bit#(1) in);
  71     (*always_ready,always_enabled*) method  Action twi_scl_outen (Bit#(1) in);
  72     (*always_ready,always_enabled*) method  Bit#(1) twi_scl_in;
  73       endinterface
  74
  75
  76    interface Ifc_pinmux;
  77       // this interface controls how each IO cell is routed.  setting
  78       // any given IO cell's mux control value will result in redirection
  79       // of not just the input or output to different peripheral functions
  80       // but also the *direction* control - if appropriate - as well.
  81       interface MuxSelectionLines mux_lines;
  82
  83       // this interface contains the inputs, outputs and direction-control
  84       // lines for all peripherals.  GPIO is considered to also be just
  85       // a peripheral because it also has in, out and direction-control.
  86       interface PeripheralSide peripheral_side;
  87
  88       // this interface is to be linked to the individual IO cells.
  89       // if looking at a "non-muxed" GPIO design, basically the
  90       // IO cell input, output and direction-control wires are cut
  91       // (giving six pairs of dangling wires, named left and right)
  92       // these iocells are routed in their place on one side ("left")
  93       // and the matching *GPIO* peripheral interfaces in/out/dir
  94       // connect to the OTHER side ("right").  the result is that
  95       // the muxer settings end up controlling the routing of where
  96       // the I/O from the IOcell actually goes.
  97       interface IOCellSide iocell_side;
  98    endinterface
  99    (*synthesize*)
 100    module mkpinmux(Ifc_pinmux);
 101
 102       // the followins wires capture the pin-mux selection
 103       // values for each mux assigned to a CELL
 104
 105       Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
 106       Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
 107       Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
 108       // following wires capture signals to IO CELL if io-0 is
 109       // allotted to it
 110       Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
 111       Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
 112       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
 113
 114       // following wires capture signals to IO CELL if io-1 is
 115       // allotted to it
 116       Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
 117       Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
 118       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
 119
 120       // following wires capture signals to IO CELL if io-2 is
 121       // allotted to it
 122       Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
 123       Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
 124       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
 125
 126       // following wires capture signals to IO CELL if uart-0 is
 127       // allotted to it
 128       Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
 129       Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
 130
 131       // following wires capture signals to IO CELL if gpioa-0 is
 132       // allotted to it
 133       Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
 134       Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
 135       Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
 136       Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
 137       Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
 138       Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
 139       Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
 140       Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
 141       Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
 142
 143       // following wires capture signals to IO CELL if twi-0 is
 144       // allotted to it
 145       Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
 146       Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
 147       Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
 148       Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
 149       Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
 150       Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
 151
 152
 153       /*====== This where the muxing starts for each io-cell======*/
 154       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 155        // output muxer for cell idx 0
 156       cell0_mux_out=
 157                         wrcell0_mux==0?wrgpioa_a0_out:
 158                         wrcell0_mux==1?wruart_tx:
 159                         wrcell0_mux==2?val0: // unused
 160                         wrtwi_sda_out;
 161
 162       // outen muxer for cell idx 0
 163       cell0_mux_outen=
 164                         wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
 165                         wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
 166                         wrcell0_mux==2?val0: // unused
 167                         wrtwi_sda_outen; // bi-directional
 168
 169       // priority-in-muxer for cell idx 0
 170       rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
 171         wrgpioa_a0_in<=cell0_mux_in;
 172       endrule
 173
 174       rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
 175         wrtwi_sda_in<=cell0_mux_in;
 176       endrule
 177
 178       // output muxer for cell idx 1
 179       cell1_mux_out=
 180                         wrcell1_mux==0?wrgpioa_a1_out:
 181                         wrcell1_mux==1?val0: // uart_rx is an input
 182                         wrcell1_mux==2?wrtwi_sda_out:
 183                         val0; // unused
 184
 185       // outen muxer for cell idx 1
 186       cell1_mux_outen=
 187                         wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
 188                         wrcell1_mux==1?val0: // uart_rx is an input
 189                         wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
 190                         val0; // unused
 191
 192       // priority-in-muxer for cell idx 1
 193       rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
 194         wrgpioa_a1_in<=cell1_mux_in;
 195       endrule
 196
 197       rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
 198         wruart_rx<=cell1_mux_in;
 199       endrule
 200
 201       rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
 202         wrtwi_sda_in<=cell1_mux_in;
 203       endrule
 204
 205       // output muxer for cell idx 2
 206       cell2_mux_out=
 207                         wrcell2_mux==0?wrgpioa_a2_out:
 208                         wrcell2_mux==1?val0: // unused
 209                         wrcell2_mux==2?wrtwi_scl_out:
 210                         val0; // unused
 211
 212       // outen muxer for cell idx 2
 213       cell2_mux_outen=
 214                         wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
 215                         wrcell2_mux==1?val0: // unused
 216                         wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
 217                         val0; // unused
 218
 219       // priority-in-muxer for cell idx 2
 220       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
 221         wrgpioa_a2_in<=cell2_mux_in;
 222       endrule
 223
 224       rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
 225         wrtwi_scl_in<=cell2_mux_in;
 226       endrule
 227
 228
 229       /*=========================================*/
 230       // dedicated cells
 231
 232
 233       /*============================================================*/
 234
 235     interface mux_lines = interface MuxSelectionLines
 236
 237       method Action  cell0_mux(Bit#(2) in);
 238          wrcell0_mux<=in;
 239       endmethod
 240
 241       method Action  cell1_mux(Bit#(2) in);
 242          wrcell1_mux<=in;
 243       endmethod
 244
 245       method Action  cell2_mux(Bit#(2) in);
 246          wrcell2_mux<=in;
 247       endmethod
 248
 249     endinterface;
 250     interface iocell_side = interface IOCellSide
 251
 252       method io0_cell_out=cell0_mux_out;
 253       method io0_cell_outen=cell0_mux_outen;
 254       method Action  io0_cell_in(Bit#(1) in);
 255          cell0_mux_in<=in;
 256       endmethod
 257
 258       method io1_cell_out=cell1_mux_out;
 259       method io1_cell_outen=cell1_mux_outen;
 260       method Action  io1_cell_in(Bit#(1) in);
 261          cell1_mux_in<=in;
 262       endmethod
 263
 264       method io2_cell_out=cell2_mux_out;
 265       method io2_cell_outen=cell2_mux_outen;
 266       method Action  io2_cell_in(Bit#(1) in);
 267          cell2_mux_in<=in;
 268       endmethod
 269
 270      endinterface;
 271     interface peripheral_side = interface PeripheralSide
 272
 273       method Action  uart_tx(Bit#(1) in);
 274          wruart_tx<=in;
 275       endmethod
 276       method uart_rx=wruart_rx;
 277
 278       method Action  gpioa_a0_out(Bit#(1) in);
 279          wrgpioa_a0_out<=in;
 280       endmethod
 281       method Action  gpioa_a0_outen(Bit#(1) in);
 282          wrgpioa_a0_outen<=in;
 283       endmethod
 284       method gpioa_a0_in=wrgpioa_a0_in;
 285       method Action  gpioa_a1_out(Bit#(1) in);
 286          wrgpioa_a1_out<=in;
 287       endmethod
 288       method Action  gpioa_a1_outen(Bit#(1) in);
 289          wrgpioa_a1_outen<=in;
 290       endmethod
 291       method gpioa_a1_in=wrgpioa_a1_in;
 292       method Action  gpioa_a2_out(Bit#(1) in);
 293          wrgpioa_a2_out<=in;
 294       endmethod
 295       method Action  gpioa_a2_outen(Bit#(1) in);
 296          wrgpioa_a2_outen<=in;
 297       endmethod
 298       method gpioa_a2_in=wrgpioa_a2_in;
 299
 300       method Action  twi_sda_out(Bit#(1) in);
 301          wrtwi_sda_out<=in;
 302       endmethod
 303       method Action  twi_sda_outen(Bit#(1) in);
 304          wrtwi_sda_outen<=in;
 305       endmethod
 306       method twi_sda_in=wrtwi_sda_in;
 307       method Action  twi_scl_out(Bit#(1) in);
 308          wrtwi_scl_out<=in;
 309       endmethod
 310       method Action  twi_scl_outen(Bit#(1) in);
 311          wrtwi_scl_outen<=in;
 312       endmethod
 313       method twi_scl_in=wrtwi_scl_in;
 314
 315      endinterface;
 316    endmodule
 317 endpackage