src/test_bsv/pinmux.bsv

   1
   2 /*
   3    This BSV file has been generated by the PinMux tool available at:
   4    https://bitbucket.org/casl/pinmux.
   5
   6    Authors: Neel Gala, Luke
   7    Date of generation: Mon Jun 25 15:11:57 2018
   8 */
   9
  10 package pinmux;
  11
  12    interface MuxSelectionLines;
  13
  14       // declare the method which will capture the user pin-mux
  15       // selection values.The width of the input is dependent on the number
  16       // of muxes happening per IO. For now we have a generalized width
  17       // where each IO will have the same number of muxes.
  18      method  Action cell0_mux (Bit#(2) in);
  19      method  Action cell1_mux (Bit#(2) in);
  20      method  Action cell2_mux (Bit#(2) in);
  21       endinterface
  22
  23
  24       interface PeripheralSide;
  25       // declare the interface to the peripherals
  26       // Each IO cell will have 3 input field (output from pin mux
  27       // and on output field (input to pinmux)
  28           // interface declaration between IO-0 and pinmux
  29     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_out;
  30     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_outen;
  31     (*always_ready,always_enabled,result="io"*) method
  32                        Action io0_cell_in (Bit#(1) in);
  33           // interface declaration between IO-1 and pinmux
  34     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_out;
  35     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_outen;
  36     (*always_ready,always_enabled,result="io"*) method
  37                        Action io1_cell_in (Bit#(1) in);
  38           // interface declaration between IO-2 and pinmux
  39     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_out;
  40     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_outen;
  41     (*always_ready,always_enabled,result="io"*) method
  42                        Action io2_cell_in (Bit#(1) in);
  43       endinterface
  44
  45
  46       interface IOCellSide;
  47       // declare the interface to the IO cells.
  48       // Each IO cell will have 3 input field (output from pin mux
  49       // and on output field (input to pinmux)
  50           // interface declaration between UART-0 and pinmux
  51     (*always_ready,always_enabled*) method  Action uart_tx (Bit#(1) in);
  52     (*always_ready,always_enabled*) method  Bit#(1) uart_rx;
  53           // interface declaration between GPIOA-0 and pinmux
  54     (*always_ready,always_enabled*) method  Action gpioa_a0_out (Bit#(1) in);
  55     (*always_ready,always_enabled*) method  Action gpioa_a0_outen (Bit#(1) in);
  56     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a0_in;
  57     (*always_ready,always_enabled*) method  Action gpioa_a1_out (Bit#(1) in);
  58     (*always_ready,always_enabled*) method  Action gpioa_a1_outen (Bit#(1) in);
  59     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a1_in;
  60     (*always_ready,always_enabled*) method  Action gpioa_a2_out (Bit#(1) in);
  61     (*always_ready,always_enabled*) method  Action gpioa_a2_outen (Bit#(1) in);
  62     (*always_ready,always_enabled*) method  Bit#(1) gpioa_a2_in;
  63           // interface declaration between TWI-0 and pinmux
  64     (*always_ready,always_enabled*) method  Action twi_sda_out (Bit#(1) in);
  65     (*always_ready,always_enabled*) method  Action twi_sda_outen (Bit#(1) in);
  66     (*always_ready,always_enabled*) method  Bit#(1) twi_sda_in;
  67     (*always_ready,always_enabled*) method  Action twi_scl_out (Bit#(1) in);
  68     (*always_ready,always_enabled*) method  Action twi_scl_outen (Bit#(1) in);
  69     (*always_ready,always_enabled*) method  Bit#(1) twi_scl_in;
  70       endinterface
  71
  72
  73    interface Ifc_pinmux;
  74       interface MuxSelectionLines mux_lines;
  75       interface PeripheralSide peripheral_side;
  76       interface IOCellSide iocell_side;
  77    endinterface
  78    (*synthesize*)
  79    module mkpinmux(Ifc_pinmux);
  80
  81       // the followins wires capture the pin-mux selection
  82       // values for each mux assigned to a CELL
  83
  84       Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
  85       Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
  86       Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
  87       // following wires capture signals to IO CELL if io-0 is
  88       // allotted to it
  89       Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
  90       Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
  91       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
  92
  93       // following wires capture signals to IO CELL if io-1 is
  94       // allotted to it
  95       Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
  96       Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
  97       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
  98
  99       // following wires capture signals to IO CELL if io-2 is
 100       // allotted to it
 101       Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
 102       Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
 103       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
 104
 105       // following wires capture signals to IO CELL if uart-0 is
 106       // allotted to it
 107       Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
 108       Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
 109
 110       // following wires capture signals to IO CELL if gpioa-0 is
 111       // allotted to it
 112       Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
 113       Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
 114       Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
 115       Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
 116       Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
 117       Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
 118       Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
 119       Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
 120       Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
 121
 122       // following wires capture signals to IO CELL if twi-0 is
 123       // allotted to it
 124       Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
 125       Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
 126       Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
 127       Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
 128       Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
 129       Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
 130
 131
 132       /*====== This where the muxing starts for each io-cell======*/
 133        // output muxer for cell idx 0
 134       cell0_mux_out=
 135                         wrcell0_mux==0?wrgpioa_a0_out:
 136                         wrcell0_mux==1?wruart_tx_out:
 137                         wrcell0_mux==2?0: // unused
 138                         0; // unused
 139
 140       // outen muxer for cell idx 0
 141       cell0_mux_outen=
 142                         wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
 143                         wrcell0_mux==1?1: // uart_tx is an output
 144                         wrcell0_mux==2?0: // unused
 145                         0; // unused
 146
 147       rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
 148         wrgpioa_a0_in<=cell0_mux_in;
 149       endrule
 150
 151       // output muxer for cell idx 1
 152       cell1_mux_out=
 153                         wrcell1_mux==0?wrgpioa_a1_out:
 154                         wrcell1_mux==1?0: // uart_rx is an input
 155                         wrcell1_mux==2?wrtwi_sda_out:
 156                         0; // unused
 157
 158       // outen muxer for cell idx 1
 159       cell1_mux_outen=
 160                         wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
 161                         wrcell1_mux==1?0: // uart_rx is an input
 162                         wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
 163                         0; // unused
 164
 165       rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
 166         wrgpioa_a1_in<=cell1_mux_in;
 167       endrule
 168
 169
 170       rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
 171         wruart_rx<=cell1_mux_in;
 172       endrule
 173
 174
 175       rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
 176         wrtwi_sda_in<=cell1_mux_in;
 177       endrule
 178
 179       // output muxer for cell idx 2
 180       cell2_mux_out=
 181                         wrcell2_mux==0?wrgpioa_a2_out:
 182                         wrcell2_mux==1?0: // unused
 183                         wrcell2_mux==2?wrtwi_scl_out:
 184                         0; // unused
 185
 186       // outen muxer for cell idx 2
 187       cell2_mux_outen=
 188                         wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
 189                         wrcell2_mux==1?0: // unused
 190                         wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
 191                         0; // unused
 192
 193       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
 194         wrgpioa_a2_in<=cell2_mux_in;
 195       endrule
 196
 197
 198       rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
 199         wrtwi_scl_in<=cell2_mux_in;
 200       endrule
 201
 202
 203       /*============================================================*/
 204
 205     interface mux_lines = interface MuxSelectionLines
 206
 207       method Action  cell0_mux(Bit#(2) in);
 208          wrcell0_mux<=in;
 209       endmethod
 210
 211       method Action  cell1_mux(Bit#(2) in);
 212          wrcell1_mux<=in;
 213       endmethod
 214
 215       method Action  cell2_mux(Bit#(2) in);
 216          wrcell2_mux<=in;
 217       endmethod
 218
 219     endinterface;
 220     interface iocell_side = interface IOCellSide
 221
 222       method io0_cell_out=cell0_mux_out;
 223       method io0_cell_outen=cell0_mux_outen;
 224       method Action  io0_cell_in(Bit#(1) in);
 225          cell0_mux_in<=in;
 226       endmethod
 227
 228       method io1_cell_out=cell1_mux_out;
 229       method io1_cell_outen=cell1_mux_outen;
 230       method Action  io1_cell_in(Bit#(1) in);
 231          cell1_mux_in<=in;
 232       endmethod
 233
 234       method io2_cell_out=cell2_mux_out;
 235       method io2_cell_outen=cell2_mux_outen;
 236       method Action  io2_cell_in(Bit#(1) in);
 237          cell2_mux_in<=in;
 238       endmethod
 239
 240      endinterface;
 241     interface peripheral_side = interface PeripheralSide
 242
 243       method Action  uart_tx(Bit#(1) in);
 244          wruart_tx<=in;
 245       endmethod
 246       method uart_rx=wruart_rx;
 247
 248       method Action  gpioa_a0_out(Bit#(1) in);
 249          wrgpioa_a0_out<=in;
 250       endmethod
 251       method Action  gpioa_a0_outen(Bit#(1) in);
 252          wrgpioa_a0_outen<=in;
 253       endmethod
 254       method gpioa_a0_in=wrgpioa_a0_in;
 255       method Action  gpioa_a1_out(Bit#(1) in);
 256          wrgpioa_a1_out<=in;
 257       endmethod
 258       method Action  gpioa_a1_outen(Bit#(1) in);
 259          wrgpioa_a1_outen<=in;
 260       endmethod
 261       method gpioa_a1_in=wrgpioa_a1_in;
 262       method Action  gpioa_a2_out(Bit#(1) in);
 263          wrgpioa_a2_out<=in;
 264       endmethod
 265       method Action  gpioa_a2_outen(Bit#(1) in);
 266          wrgpioa_a2_outen<=in;
 267       endmethod
 268       method gpioa_a2_in=wrgpioa_a2_in;
 269
 270       method Action  twi_sda_out(Bit#(1) in);
 271          wrtwi_sda_out<=in;
 272       endmethod
 273       method Action  twi_sda_outen(Bit#(1) in);
 274          wrtwi_sda_outen<=in;
 275       endmethod
 276       method twi_sda_in=wrtwi_sda_in;
 277       method Action  twi_scl_out(Bit#(1) in);
 278          wrtwi_scl_out<=in;
 279       endmethod
 280       method Action  twi_scl_outen(Bit#(1) in);
 281          wrtwi_scl_outen<=in;
 282       endmethod
 283       method twi_scl_in=wrtwi_scl_in;
 284
 285      endinterface;
 286    endmodule
 287 endpackage