src/test_bsv/pinmux_experiment.bsv

   1
   2 /*
   3    This BSV file has been generated by the PinMux tool available at:
   4    https://bitbucket.org/casl/pinmux.
   5
   6    Authors: Neel Gala, Luke
   7    Date of generation: Sun Jul 22 05:31:10 2018
   8 */
   9
  10 package pinmux_experiment;
  11
  12 import GetPut::*;
  13
  14       (*always_ready,always_enabled*)
  15       interface MuxSelectionLines;
  16
  17       // declare the method which will capture the user pin-mux
  18       // selection values.The width of the input is dependent on the number
  19       // of muxes happening per IO. For now we have a generalized width
  20       // where each IO will have the same number of muxes.
  21      method  Action cell0_mux (Bit#(2) in);
  22      method  Action cell1_mux (Bit#(2) in);
  23      method  Action cell2_mux (Bit#(2) in);
  24       endinterface
  25
  26
  27       interface IOCellSide;
  28       // declare the interface to the IO cells.
  29       // Each IO cell will have 1 input field (output from pin mux)
  30       // and an output and out-enable field (input to pinmux)
  31           // interface declaration between IO-0 and pinmux
  32     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_out;
  33     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_outen;
  34     (*always_ready,always_enabled,result="io"*) method
  35                        Action io0_cell_in (Bit#(1) in);
  36           // interface declaration between IO-1 and pinmux
  37     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_out;
  38     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_outen;
  39     (*always_ready,always_enabled,result="io"*) method
  40                        Action io1_cell_in (Bit#(1) in);
  41           // interface declaration between IO-2 and pinmux
  42     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_out;
  43     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_outen;
  44     (*always_ready,always_enabled,result="io"*) method
  45                        Action io2_cell_in (Bit#(1) in);
  46       endinterface
  47
  48       // interface declaration between UART and pinmux
  49       (*always_ready,always_enabled*)
  50       interface PeripheralSideUART;
  51           interface Put#(Bit#(1)) tx;
  52           interface Get#(Bit#(1)) rx;
  53       endinterface
  54
  55       // interface declaration between GPIOA and pinmux
  56       (*always_ready,always_enabled*)
  57       interface PeripheralSideGPIOA;
  58           interface Put#(Bit#(1)) a0_out;
  59           interface Put#(Bit#(1)) a0_outen;
  60           interface Get#(Bit#(1)) a0_in;
  61           interface Put#(Bit#(1)) a1_out;
  62           interface Put#(Bit#(1)) a1_outen;
  63           interface Get#(Bit#(1)) a1_in;
  64           interface Put#(Bit#(1)) a2_out;
  65           interface Put#(Bit#(1)) a2_outen;
  66           interface Get#(Bit#(1)) a2_in;
  67       endinterface
  68
  69       // interface declaration between TWI and pinmux
  70       (*always_ready,always_enabled*)
  71       interface PeripheralSideTWI;
  72           interface Put#(Bit#(1)) sda_out;
  73           interface Put#(Bit#(1)) sda_outen;
  74           interface Get#(Bit#(1)) sda_in;
  75           interface Put#(Bit#(1)) scl_out;
  76           interface Put#(Bit#(1)) scl_outen;
  77           interface Get#(Bit#(1)) scl_in;
  78       endinterface
  79
  80       (*always_ready,always_enabled*)
  81       interface PeripheralSide;
  82       // declare the interface to the peripherals
  83       // Each peripheral's function will be either an input, output
  84       // or be bi-directional.  an input field will be an output from the
  85       // peripheral and an output field will be an input to the peripheral.
  86       // Bi-directional functions also have an output-enable (which
  87       // again comes *in* from the peripheral)
  88           // interface declaration between UART-0 and pinmux
  89             interface PeripheralSideUART uart;
  90             interface PeripheralSideGPIOA gpioa;
  91             interface PeripheralSideTWI twi;
  92       endinterface
  93
  94
  95    interface Ifc_pinmux;
  96       // this interface controls how each IO cell is routed.  setting
  97       // any given IO cell's mux control value will result in redirection
  98       // of not just the input or output to different peripheral functions
  99       // but also the *direction* control - if appropriate - as well.
 100       interface MuxSelectionLines mux_lines;
 101
 102       // this interface contains the inputs, outputs and direction-control
 103       // lines for all peripherals.  GPIO is considered to also be just
 104       // a peripheral because it also has in, out and direction-control.
 105       interface PeripheralSide peripheral_side;
 106
 107       // this interface is to be linked to the individual IO cells.
 108       // if looking at a "non-muxed" GPIO design, basically the
 109       // IO cell input, output and direction-control wires are cut
 110       // (giving six pairs of dangling wires, named left and right)
 111       // these iocells are routed in their place on one side ("left")
 112       // and the matching *GPIO* peripheral interfaces in/out/dir
 113       // connect to the OTHER side ("right").  the result is that
 114       // the muxer settings end up controlling the routing of where
 115       // the I/O from the IOcell actually goes.
 116       interface IOCellSide iocell_side;
 117    endinterface
 118    (*synthesize*)
 119
 120    module mkpinmux(Ifc_pinmux);
 121
 122       // the followins wires capture the pin-mux selection
 123       // values for each mux assigned to a CELL
 124
 125       Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
 126       Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
 127       Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
 128       // following wires capture signals to IO CELL if io-0 is
 129       // allotted to it
 130       Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
 131       Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
 132       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
 133
 134       // following wires capture signals to IO CELL if io-1 is
 135       // allotted to it
 136       Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
 137       Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
 138       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
 139
 140       // following wires capture signals to IO CELL if io-2 is
 141       // allotted to it
 142       Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
 143       Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
 144       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
 145
 146       // following wires capture signals to IO CELL if uart-0 is
 147       // allotted to it
 148       Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
 149       Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
 150
 151       // following wires capture signals to IO CELL if gpioa-0 is
 152       // allotted to it
 153       Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
 154       Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
 155       Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
 156       Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
 157       Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
 158       Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
 159       Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
 160       Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
 161       Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
 162
 163       // following wires capture signals to IO CELL if twi-0 is
 164       // allotted to it
 165       Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
 166       Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
 167       Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
 168       Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
 169       Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
 170       Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
 171
 172
 173       /*====== This where the muxing starts for each io-cell======*/
 174       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 175        // output muxer for cell idx 0
 176       cell0_mux_out=
 177                         wrcell0_mux==0?wrgpioa_a0_out:
 178                         wrcell0_mux==1?wruart_tx:
 179                         wrcell0_mux==2?val0: // unused
 180                         wrtwi_sda_out;
 181
 182       // outen muxer for cell idx 0
 183       cell0_mux_outen=
 184                         wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
 185                         wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
 186                         wrcell0_mux==2?val0: // unused
 187                         wrtwi_sda_outen; // bi-directional
 188
 189       // priority-in-muxer for cell idx 0
 190       rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
 191         wrgpioa_a0_in<=cell0_mux_in;
 192       endrule
 193
 194       rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
 195         wrtwi_sda_in<=cell0_mux_in;
 196       endrule
 197
 198       // output muxer for cell idx 1
 199       cell1_mux_out=
 200                         wrcell1_mux==0?wrgpioa_a1_out:
 201                         wrcell1_mux==1?val0: // uart_rx is an input
 202                         wrcell1_mux==2?wrtwi_sda_out:
 203                         val0; // unused
 204
 205       // outen muxer for cell idx 1
 206       cell1_mux_outen=
 207                         wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
 208                         wrcell1_mux==1?val0: // uart_rx is an input
 209                         wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
 210                         val0; // unused
 211
 212       // priority-in-muxer for cell idx 1
 213       rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
 214         wrgpioa_a1_in<=cell1_mux_in;
 215       endrule
 216
 217       rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
 218         wruart_rx<=cell1_mux_in;
 219       endrule
 220
 221       rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
 222         wrtwi_sda_in<=cell1_mux_in;
 223       endrule
 224
 225       // output muxer for cell idx 2
 226       cell2_mux_out=
 227                         wrcell2_mux==0?wrgpioa_a2_out:
 228                         wrcell2_mux==1?val0: // unused
 229                         wrcell2_mux==2?wrtwi_scl_out:
 230                         val0; // unused
 231
 232       // outen muxer for cell idx 2
 233       cell2_mux_outen=
 234                         wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
 235                         wrcell2_mux==1?val0: // unused
 236                         wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
 237                         val0; // unused
 238
 239       // priority-in-muxer for cell idx 2
 240       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
 241         wrgpioa_a2_in<=cell2_mux_in;
 242       endrule
 243
 244       rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
 245         wrtwi_scl_in<=cell2_mux_in;
 246       endrule
 247
 248
 249       /*=========================================*/
 250       // dedicated cells
 251
 252
 253       /*============================================================*/
 254
 255     interface mux_lines = interface MuxSelectionLines
 256
 257       method Action  cell0_mux(Bit#(2) in);
 258          wrcell0_mux<=in;
 259       endmethod
 260
 261       method Action  cell1_mux(Bit#(2) in);
 262          wrcell1_mux<=in;
 263       endmethod
 264
 265       method Action  cell2_mux(Bit#(2) in);
 266          wrcell2_mux<=in;
 267       endmethod
 268
 269     endinterface;
 270
 271     interface iocell_side = interface IOCellSide
 272
 273       method io0_cell_out=cell0_mux_out;
 274       method io0_cell_outen=cell0_mux_outen;
 275       method Action  io0_cell_in(Bit#(1) in);
 276          cell0_mux_in<=in;
 277       endmethod
 278
 279       method io1_cell_out=cell1_mux_out;
 280       method io1_cell_outen=cell1_mux_outen;
 281       method Action  io1_cell_in(Bit#(1) in);
 282          cell1_mux_in<=in;
 283       endmethod
 284
 285       method io2_cell_out=cell2_mux_out;
 286       method io2_cell_outen=cell2_mux_outen;
 287       method Action  io2_cell_in(Bit#(1) in);
 288          cell2_mux_in<=in;
 289       endmethod
 290
 291      endinterface;
 292       interface peripheral_side= interface PeripheralSide
 293         interface uart = interface PeripheralSideUART
 294             // interface declaration between UART and pinmux
 295             interface tx = interface Put
 296               method Action put(Bit#(1) in);
 297                 wruart_tx<=in;
 298               endmethod
 299             endinterface;
 300             interface  rx = interface Get
 301               method ActionValue#(Bit#(1)) get;
 302                 return wruart_rx;
 303               endmethod
 304             endinterface;
 305         endinterface;
 306
 307         interface twi = interface PeripheralSideTWI
 308             // interface declaration between TWI and pinmux
 309             interface sda_out = interface Put
 310               method Action put(Bit#(1) in);
 311                 wrtwi_sda_out<=in;
 312               endmethod
 313             endinterface;
 314             interface sda_outen = interface Put
 315               method Action put(Bit#(1) in);
 316                 wrtwi_sda_outen<=in;
 317               endmethod
 318             endinterface;
 319             interface  sda_in = interface Get
 320               method ActionValue#(Bit#(1)) get;
 321                 return wrtwi_sda_in;
 322               endmethod
 323             endinterface;
 324             interface scl_out = interface Put
 325               method Action put(Bit#(1) in);
 326                 wrtwi_scl_out<=in;
 327               endmethod
 328             endinterface;
 329             interface scl_outen = interface Put
 330               method Action put(Bit#(1) in);
 331                 wrtwi_scl_outen<=in;
 332               endmethod
 333             endinterface;
 334             interface  scl_in = interface Get
 335               method ActionValue#(Bit#(1)) get;
 336                 return wrtwi_scl_in;
 337               endmethod
 338             endinterface;
 339          endinterface;
 340
 341         interface gpioa = interface PeripheralSideGPIOA
 342
 343             interface a0_out = interface Put
 344               method Action put(Bit#(1) in);
 345                 wrgpioa_a0_out<=in;
 346               endmethod
 347             endinterface;
 348             interface a0_outen = interface Put
 349               method Action put(Bit#(1) in);
 350                 wrgpioa_a0_outen<=in;
 351               endmethod
 352             endinterface;
 353             interface  a0_in = interface Get
 354               method ActionValue#(Bit#(1)) get;
 355                 return wrgpioa_a0_in;
 356               endmethod
 357             endinterface;
 358             interface a1_out = interface Put
 359               method Action put(Bit#(1) in);
 360                 wrgpioa_a1_out<=in;
 361               endmethod
 362             endinterface;
 363             interface a1_outen = interface Put
 364               method Action put(Bit#(1) in);
 365                 wrgpioa_a1_outen<=in;
 366               endmethod
 367             endinterface;
 368             interface  a1_in = interface Get
 369               method ActionValue#(Bit#(1)) get;
 370                 return wrgpioa_a1_in;
 371               endmethod
 372             endinterface;
 373             interface a2_out = interface Put
 374               method Action put(Bit#(1) in);
 375                 wrgpioa_a2_out<=in;
 376               endmethod
 377             endinterface;
 378             interface a2_outen = interface Put
 379               method Action put(Bit#(1) in);
 380                 wrgpioa_a2_outen<=in;
 381               endmethod
 382             endinterface;
 383             interface  a2_in = interface Get
 384               method ActionValue#(Bit#(1)) get;
 385                 return wrgpioa_a2_in;
 386               endmethod
 387             endinterface;
 388         endinterface;
 389
 390
 391       endinterface;
 392    endmodule
 393 endpackage