src/test_bsv/tests/test_pinmux.py

   1 # Simple tests for an pinmux module
   2 import cocotb
   3 from cocotb.triggers import Timer
   4 from cocotb.result import TestFailure
   5 #from pinmux_model import pinmux_model
   6 import random
   7
   8
   9 """ dut is design under test """
  10
  11 """
  12 for gpio2, there are three ports at peripheral side:
  13     peripheral_side_gpioa_a2_out_in
  14     peripheral_side_gpioa_a2_outen_in
  15     peripheral_side_gpioa_a2_in
  16 """
  17 @cocotb.test()
  18 def pinmux_gpio2(dut):
  19     """Test for GPIO2"""
  20     yield Timer(2)
  21     # mux selection lines, each input two bit wide
  22     dut.mux_lines_cell2_mux_in = 0
  23     yield Timer(2)
  24     # enable input for mux
  25     dut.EN_mux_lines_cell0_mux = 0
  26     dut.EN_mux_lines_cell1_mux = 0
  27     dut.EN_mux_lines_cell2_mux = 1
  28
  29     yield Timer(2)
  30
  31     # GPIO2-out test
  32     # GPIO is inout peripheral
  33     dut.peripheral_side_gpioa_a2_out_in = 0
  34     dut.peripheral_side_gpioa_a2_outen_in = 1
  35
  36     yield Timer(2)
  37
  38     if dut.iocell_side_io2_cell_out != 0:  # output of iopad
  39         raise TestFailure(
  40             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
  41             str(dut.iocell_side_io2_cell_out))
  42
  43     dut.peripheral_side_gpioa_a2_out_in = 1
  44
  45     yield Timer(2)
  46
  47     if dut.iocell_side_io2_cell_out != 1:
  48         raise TestFailure(
  49             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  50             str(dut.iocell_side_io2_cell_out))
  51
  52     # GPIO2-in test (first see if it's tri-state)
  53     if str(dut.peripheral_side_gpioa_a2_in) != "x":
  54         raise TestFailure(
  55             "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
  56             str(dut.peripheral_side_gpioa_a2_in))
  57
  58     dut.peripheral_side_gpioa_a2_outen_in = 0
  59     dut.iocell_side_io2_cell_in_in = 0
  60     yield Timer(2)
  61
  62     if dut.peripheral_side_gpioa_a2_in != 0:
  63         raise TestFailure(
  64             "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
  65             str(dut.peripheral_side_gpioa_a2_in))
  66
  67     dut.iocell_side_io2_cell_in_in = 1
  68     yield Timer(2)
  69
  70     if dut.peripheral_side_gpioa_a2_in != 1:
  71         raise TestFailure(
  72             "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
  73             str(dut.peripheral_side_gpioa_a2_in))
  74
  75     dut.peripheral_side_gpioa_a2_outen_in = 1
  76     dut.iocell_side_io2_cell_in_in = 0
  77     yield Timer(2)
  78     dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_gpioa_a2_in)
  79
  80     if dut.iocell_side_io2_cell_out != 1:
  81         raise TestFailure(
  82             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  83             str(dut.iocell_side_io2_cell_out))
  84
  85     dut._log.info("Ok!, gpio2 passed")
  86
  87 @cocotb.test()
  88 def pinmux_uart(dut):
  89     """Test for UART"""
  90     yield Timer(2)
  91     # mux selection lines, each input two bit wide
  92     dut.mux_lines_cell0_mux_in = 1
  93     yield Timer(2)
  94     # enable input for mux
  95     dut.EN_mux_lines_cell0_mux = 1
  96     dut.EN_mux_lines_cell1_mux = 0
  97     dut.EN_mux_lines_cell2_mux = 0
  98
  99     yield Timer(2)
 100
 101     # UART
 102     yield Timer(2)
 103     dut.peripheral_side_uart_tx_in = 1
 104     dut.peripheral_side_gpioa_a0_outen_in = 1
 105
 106     yield Timer(2)
 107
 108     if dut.iocell_side_io0_cell_out != 1:
 109         raise TestFailure(
 110             "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
 111             str(dut.iocell_side_io0_cell_out))
 112
 113     dut.peripheral_side_uart_tx_in = 0
 114
 115     yield Timer(2)
 116
 117     if dut.iocell_side_io0_cell_out != 0:
 118         raise TestFailure(
 119             "uart_tx=0/mux=0/out=1 %s iocell_io0 != 0" %
 120             str(dut.iocell_side_io0_cell_out))
 121
 122     dut._log.info("Ok!, uart passed")
 123
 124 @cocotb.test()
 125 def pinmux_twi_scl(dut):
 126     """Test for I2C SCL"""
 127     yield Timer(2)
 128     # mux selection lines, each input two bit wide
 129     dut.mux_lines_cell0_mux_in = 1
 130     dut.mux_lines_cell1_mux_in = 2
 131     dut.mux_lines_cell2_mux_in = 0
 132     yield Timer(2)
 133     # enable input for mux
 134     dut.EN_mux_lines_cell0_mux = 0
 135     dut.EN_mux_lines_cell1_mux = 1
 136     dut.EN_mux_lines_cell2_mux = 0
 137
 138     yield Timer(2)
 139
 140     # Test for out for twi_scl
 141     dut.peripheral_side_twi_scl_out_in = 0
 142     dut.peripheral_side_twi_scl_outen_in = 1
 143     yield Timer(2)
 144
 145     if dut.iocell_side_io2_cell_out != 0:
 146         raise TestFailure(
 147             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 148             str(dut.iocell_side_io2_cell_out))
 149
 150     dut.peripheral_side_twi_scl_out_in = 1
 151     yield Timer(2)
 152
 153     if dut.iocell_side_io2_cell_out != 1:
 154         raise TestFailure(
 155             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 156             str(dut.iocell_side_io2_cell_out))
 157
 158     # Test for in
 159     # first check for tristate
 160     if str(dut.peripheral_side_twi_scl_in) != "x":
 161         raise TestFailure(
 162             "twi_scl=0/mux=0/out=1 %s twi_scl_in != x" %
 163             str(dut.peripheral_side_twi_scl_in))
 164
 165     dut.peripheral_side_twi_scl_outen_in = 0
 166     dut.iocell_side_io2_cell_in_in = 0
 167     yield Timer(2)
 168
 169     if dut.peripheral_side_twi_scl_in != 0:
 170         raise TestFailure(
 171             "iocell_io2=0/mux=0/out=0 %s twi_scl != 0" %
 172             str(dut.peripheral_side_twi_scl_in))
 173
 174     dut.iocell_side_io2_cell_in_in = 1
 175     yield Timer(2)
 176
 177     if dut.peripheral_side_twi_scl_in != 1:
 178         raise TestFailure(
 179             "iocell_io2=1/mux=0/out=0 %s twi_scl != 1" %
 180             str(dut.peripheral_side_twi_scl_in))
 181
 182     dut.peripheral_side_twi_scl_outen_in = 1
 183     dut.iocell_side_io2_cell_in_in = 0
 184     yield Timer(2)
 185     dut._log.info("twi_scl_in %s" % dut.peripheral_side_twi_scl_in)
 186
 187     if dut.iocell_side_io2_cell_out != 1:
 188         raise TestFailure(
 189             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 1" %
 190             str(dut.iocell_side_io2_cell_out))
 191
 192     yield Timer(2)
 193
 194     dut._log.info("Ok!, twi_scl passed")
 195
 196 @cocotb.test()
 197 def pinmux_twi_sda(dut):
 198     """Test for I2C"""
 199     yield Timer(2)
 200     # mux selection lines, each input two bit wide
 201     dut.mux_lines_cell1_mux_in = 2
 202     yield Timer(2)
 203     # enable input for mux
 204     dut.EN_mux_lines_cell0_mux = 0
 205     dut.EN_mux_lines_cell1_mux = 1
 206     dut.EN_mux_lines_cell2_mux = 0
 207
 208     yield Timer(2)
 209
 210     # TWI
 211     yield Timer(2)
 212     # define input variables
 213     dut.peripheral_side_twi_sda_out_in = 0
 214     dut.peripheral_side_twi_sda_outen_in = 1
 215
 216     yield Timer(2)
 217
 218     dut._log.info("io1_out %s" % dut.iocell_side_io1_cell_out)
 219     # Test for out for twi_sda
 220     if dut.iocell_side_io1_cell_out != 0:
 221         raise TestFailure(
 222             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 0" %
 223             str(dut.iocell_side_io1_cell_out))
 224
 225     dut.peripheral_side_twi_sda_out_in = 1
 226     yield Timer(2)
 227
 228     if dut.iocell_side_io1_cell_out != 1:
 229         raise TestFailure(
 230             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 231             str(dut.iocell_side_io1_cell_out))
 232
 233     # Test for in
 234     # first check for tristate
 235     if str(dut.peripheral_side_twi_sda_in) != "x":
 236         raise TestFailure(
 237             "twi_sda=0/mux=0/out=1 %s twi_sda_in != x" %
 238             str(dut.peripheral_side_twi_sda_in))
 239
 240     dut.peripheral_side_twi_sda_outen_in = 0
 241     dut.iocell_side_io1_cell_in_in = 0
 242     yield Timer(2)
 243
 244     if dut.peripheral_side_twi_sda_in != 0:
 245         raise TestFailure(
 246             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 247             str(dut.peripheral_side_twi_sda_in))
 248
 249     dut.iocell_side_io1_cell_in_in = 1
 250     yield Timer(2)
 251
 252     if dut.peripheral_side_twi_sda_in != 1:
 253         raise TestFailure(
 254             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 255             str(dut.peripheral_side_twi_sda_in))
 256
 257     dut.peripheral_side_twi_sda_outen_in = 1
 258     dut.iocell_side_io1_cell_in_in = 0
 259     yield Timer(2)
 260     dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
 261
 262     if dut.iocell_side_io1_cell_out != 1:
 263         raise TestFailure(
 264             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 1" %
 265             str(dut.iocell_side_io1_cell_out))
 266
 267     yield Timer(2)
 268
 269     dut._log.info("Ok!, twi_sda passed")