src/test_bsv/tests/test_pinmux.py

   1 # Simple tests for an pinmux module
   2 import cocotb
   3 from cocotb.triggers import Timer
   4 from cocotb.result import TestFailure
   5 #from pinmux_model import pinmux_model
   6 import random
   7
   8
   9 """ dut is design under test """
  10
  11 """
  12 for gpio2, there are three ports at peripheral side:
  13     peripheral_side_gpioa_a2_out_in
  14     peripheral_side_gpioa_a2_outen_in
  15     peripheral_side_gpioa_a2_in
  16 """
  17
  18
  19 @cocotb.test()
  20 def pinmux_gpio2(dut):
  21     """Test for GPIO2"""
  22     yield Timer(2)
  23     # mux selection lines, each input two bit wide
  24     dut.mux_lines_cell2_mux_in = 0
  25     yield Timer(2)
  26     # enable input for mux
  27     dut.EN_mux_lines_cell0_mux = 0
  28     dut.EN_mux_lines_cell1_mux = 0
  29     dut.EN_mux_lines_cell2_mux = 1
  30
  31     yield Timer(2)
  32
  33     # GPIO2-out test
  34     # GPIO is inout peripheral
  35     dut.peripheral_side_gpioa_a2_out_in = 0
  36     dut.peripheral_side_gpioa_a2_outen_in = 1
  37
  38     yield Timer(2)
  39
  40     if dut.iocell_side_io2_cell_out != 0:  # output of iopad
  41         raise TestFailure(
  42             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
  43             str(dut.iocell_side_io2_cell_out))
  44
  45     dut.peripheral_side_gpioa_a2_out_in = 1
  46
  47     yield Timer(2)
  48
  49     if dut.iocell_side_io2_cell_out != 1:
  50         raise TestFailure(
  51             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  52             str(dut.iocell_side_io2_cell_out))
  53
  54     # GPIO2-in test (first see if it's tri-state)
  55     #
  56     if str(dut.peripheral_side_gpioa_a2_in) != "x":
  57         raise TestFailure(
  58             "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
  59             str(dut.peripheral_side_gpioa_a2_in))
  60
  61     dut.peripheral_side_gpioa_a2_outen_in = 0
  62     dut.iocell_side_io2_cell_in_in = 0
  63     yield Timer(2)
  64
  65     if dut.peripheral_side_gpioa_a2_in != 0:
  66         raise TestFailure(
  67             "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
  68             str(dut.peripheral_side_gpioa_a2_in))
  69
  70     dut.iocell_side_io2_cell_in_in = 1
  71     yield Timer(2)
  72
  73     if dut.peripheral_side_gpioa_a2_in != 1:
  74         raise TestFailure(
  75             "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
  76             str(dut.peripheral_side_gpioa_a2_in))
  77
  78     dut.peripheral_side_gpioa_a2_outen_in = 1
  79     dut.iocell_side_io2_cell_in_in = 0
  80     yield Timer(2)
  81     dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_gpioa_a2_in)
  82
  83     if dut.iocell_side_io2_cell_out != 1:
  84         raise TestFailure(
  85             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  86             str(dut.iocell_side_io2_cell_out))
  87
  88     dut._log.info("Ok!, gpio2 passed")
  89
  90
  91 @cocotb.test()
  92 def pinmux_uart(dut):
  93     """Test for UART"""
  94     yield Timer(2)
  95     # mux selection lines, each input two bit wide
  96     dut.mux_lines_cell0_mux_in = 1
  97     yield Timer(2)
  98     # enable input for mux
  99     dut.EN_mux_lines_cell0_mux = 1
 100     dut.EN_mux_lines_cell1_mux = 0
 101     dut.EN_mux_lines_cell2_mux = 0
 102
 103     # UART
 104     yield Timer(2)
 105     dut.peripheral_side_uart_tx_in = 1
 106     dut.peripheral_side_gpioa_a0_outen_in = 1
 107
 108     yield Timer(2)
 109
 110     if dut.iocell_side_io0_cell_out != 1:
 111         raise TestFailure(
 112             "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
 113             str(dut.iocell_side_io0_cell_out))
 114
 115     dut.peripheral_side_uart_tx_in = 0
 116
 117     yield Timer(2)
 118
 119     if dut.iocell_side_io0_cell_out != 0:
 120         raise TestFailure(
 121             "uart_tx=0/mux=0/out=1 %s iocell_io0 != 0" %
 122             str(dut.iocell_side_io0_cell_out))
 123
 124     dut._log.info("Ok!, uart passed")
 125
 126
 127 @cocotb.test()
 128 def pinmux_twi_scl(dut):
 129     """Test for I2C SCL"""
 130     yield Timer(2)
 131     # mux selection lines, each input two bit wide
 132     dut.mux_lines_cell2_mux_in = 2
 133     yield Timer(2)
 134     # enable input for mux
 135     dut.EN_mux_lines_cell0_mux = 0
 136     dut.EN_mux_lines_cell1_mux = 0
 137     dut.EN_mux_lines_cell2_mux = 1
 138
 139     yield Timer(2)
 140
 141     # Test for out for twi_scl
 142     dut.peripheral_side_twi_scl_out_in = 0
 143     dut.peripheral_side_twi_scl_outen_in = 1
 144     yield Timer(2)
 145
 146     if dut.iocell_side_io2_cell_out != 0:
 147         raise TestFailure(
 148             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 149             str(dut.iocell_side_io2_cell_out))
 150
 151     dut.peripheral_side_twi_scl_out_in = 1
 152     yield Timer(2)
 153
 154     if dut.iocell_side_io2_cell_out != 1:
 155         raise TestFailure(
 156             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 157             str(dut.iocell_side_io2_cell_out))
 158
 159     dut._log.info("twi_scl_in %s" % dut.peripheral_side_twi_scl_in)
 160
 161     # Test for in
 162     dut.peripheral_side_twi_scl_outen_in = 0
 163     dut.iocell_side_io2_cell_in_in = 0
 164     yield Timer(2)
 165
 166     if dut.peripheral_side_twi_scl_in != 0:
 167         raise TestFailure(
 168             "iocell_io2=0/mux=0/out=0 %s twi_scl != 0" %
 169             str(dut.peripheral_side_twi_scl_in))
 170
 171     dut.iocell_side_io2_cell_in_in = 1
 172     yield Timer(2)
 173
 174     if dut.peripheral_side_twi_scl_in != 1:
 175         raise TestFailure(
 176             "iocell_io2=1/mux=0/out=0 %s twi_scl != 1" %
 177             str(dut.peripheral_side_twi_scl_in))
 178
 179     dut.peripheral_side_twi_scl_outen_in = 1
 180     dut.iocell_side_io2_cell_in_in = 0
 181     yield Timer(2)
 182     dut._log.info("twi_scl_in %s" % dut.peripheral_side_twi_scl_in)
 183
 184     if dut.iocell_side_io2_cell_out != 1:
 185         raise TestFailure(
 186             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 1" %
 187             str(dut.iocell_side_io2_cell_out))
 188
 189     yield Timer(2)
 190
 191     dut._log.info("Ok!, twi_scl passed")
 192
 193
 194 @cocotb.test()
 195 def pinmux_twi_sda(dut):
 196     """Test for I2C"""
 197     yield Timer(2)
 198     # mux selection lines, each input two bit wide
 199     dut.mux_lines_cell1_mux_in = 2
 200     yield Timer(2)
 201     # enable input for mux
 202     dut.EN_mux_lines_cell0_mux = 0
 203     dut.EN_mux_lines_cell1_mux = 1
 204     dut.EN_mux_lines_cell2_mux = 0
 205
 206     # TWI
 207     yield Timer(2)
 208     # define input variables
 209     dut.peripheral_side_twi_sda_out_in = 0
 210     dut.peripheral_side_twi_sda_outen_in = 1
 211
 212     yield Timer(2)
 213
 214     dut._log.info("io1_out %s" % dut.iocell_side_io1_cell_out)
 215     # Test for out for twi_sda
 216     if dut.iocell_side_io1_cell_out != 0:
 217         raise TestFailure(
 218             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 0" %
 219             str(dut.iocell_side_io1_cell_out))
 220
 221     dut.peripheral_side_twi_sda_out_in = 1
 222     yield Timer(2)
 223
 224     if dut.iocell_side_io1_cell_out != 1:
 225         raise TestFailure(
 226             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 227             str(dut.iocell_side_io1_cell_out))
 228
 229     dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
 230
 231     # Test for in
 232     dut.peripheral_side_twi_sda_outen_in = 0
 233     dut.iocell_side_io1_cell_in_in = 0
 234     yield Timer(2)
 235
 236     if dut.peripheral_side_twi_sda_in != 0:
 237         raise TestFailure(
 238             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 239             str(dut.peripheral_side_twi_sda_in))
 240
 241     dut.iocell_side_io1_cell_in_in = 1
 242     yield Timer(2)
 243
 244     if dut.peripheral_side_twi_sda_in != 1:
 245         raise TestFailure(
 246             "iocell_io1=1/mux=0/out=0 %s twi_sda != 1" %
 247             str(dut.peripheral_side_twi_sda_in))
 248
 249     dut.peripheral_side_twi_sda_outen_in = 1
 250     dut.iocell_side_io1_cell_in_in = 0
 251     yield Timer(2)
 252     dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
 253
 254     if dut.iocell_side_io1_cell_out != 1:
 255         raise TestFailure(
 256             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 1" %
 257             str(dut.iocell_side_io1_cell_out))
 258
 259     yield Timer(2)
 260
 261     dut._log.info("Ok!, twi_sda passed")
 262
 263
 264 @cocotb.test()
 265 def pinmux_twi_sda2(dut):
 266     """Test for I2C multi-input (route 2 inputs to same function)
 267     """
 268     yield Timer(2)
 269     # mux selection lines, each input two bit wide
 270     dut.mux_lines_cell1_mux_in = 2
 271     yield Timer(2)
 272     # enable input for mux
 273     dut.EN_mux_lines_cell0_mux = 0
 274     dut.EN_mux_lines_cell1_mux = 1
 275     dut.EN_mux_lines_cell2_mux = 0
 276
 277     # TWI
 278     yield Timer(2)
 279     # Test for in
 280     dut.peripheral_side_twi_sda_outen_in = 0
 281     dut.iocell_side_io1_cell_in_in = 0
 282     yield Timer(2)
 283
 284     if dut.peripheral_side_twi_sda_in != 0:
 285         raise TestFailure(
 286             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 287             str(dut.peripheral_side_twi_sda_in))
 288
 289     dut.iocell_side_io1_cell_in_in = 1
 290     yield Timer(2)
 291
 292     if dut.peripheral_side_twi_sda_in != 1:
 293         raise TestFailure(
 294             "iocell_io1=1/mux=0/out=0 %s twi_sda != 1" %
 295             str(dut.peripheral_side_twi_sda_in))
 296
 297     dut.iocell_side_io1_cell_in_in = 0
 298     yield Timer(2)
 299     dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
 300
 301     if dut.peripheral_side_twi_sda_in != 0:
 302         raise TestFailure(
 303             "iocell_io1=1/mux=0/out=0 %s twi_sda != 0" %
 304             str(dut.peripheral_side_twi_sda_in))
 305
 306     # ok now set up gpioa0, set it to the opposite of twi_sda (0) i.e. gpioa0=1
 307     # and test that... then switch over pin0/mux=3
 308     dut.peripheral_side_gpioa_a0_outen_in = 0 # settings for input
 309     dut.mux_lines_cell0_mux_in = 0
 310     dut.EN_mux_lines_cell0_mux = 1
 311     dut.iocell_side_io0_cell_in_in = 1  # twi_sda=0, so gpioa0 should be 1
 312     yield Timer(2)
 313
 314     if dut.peripheral_side_gpioa_a0_in != 1:  # output of iopad
 315         raise TestFailure(
 316             "iocell_io0=1/mux=0/out=0 %s gpio_a0 != 1" %
 317             str(dut.peripheral_side_gpioa_a0_in))
 318
 319     # also twi_sda should also = 0, because.. because...
 320     # pin1 is still routed to it, and pin1 is still set to 0...
 321     if dut.peripheral_side_twi_sda_in != 0:
 322         raise TestFailure(
 323             "iocell_io0=1/mux=0/out=0 %s twi_sda != 0" %
 324             str(dut.peripheral_side_twi_sda_in))
 325
 326     # ok flip over to test 3
 327     dut.mux_lines_cell0_mux_in = 3
 328     yield Timer(2)
 329
 330     # ok now this should drop to 0 because the muxer's no longer
 331     # routing iopad0 to gpioa0...
 332     if dut.peripheral_side_gpioa_a0_in != 0:  # output of iopad
 333         raise TestFailure(
 334             "iocell_io0=1/mux=0/out=0 %s gpio_a0 != 0" %
 335             str(dut.peripheral_side_gpioa_a0_in))
 336
 337     # AND, at the same time, twi_sda should also = 1, because.. because...
 338     # pin1 is no longer routed to it, because of the priority muxer
 339     # now points pin *0* at twi_sda: that's the point of a priority
 340     # muxer, pin0 and pin1 are both pointint to twi_sda but pin0
 341     # gets precedence.
 342     if dut.peripheral_side_twi_sda_in != 1:
 343         raise TestFailure(
 344             "iocell_io0=1/mux=0/out=0 %s twi_sda != 1" %
 345             str(dut.peripheral_side_twi_sda_in))
 346
 347     # ok so now set cell1 muxer to point to gpioa1...
 348     dut.mux_lines_cell1_mux_in = 0
 349     yield Timer(2)
 350
 351     # now we test twi sda again (it shouldn't change)
 352     if dut.peripheral_side_twi_sda_in != 1:
 353         raise TestFailure(
 354             "iocell_io0=1/mux=0/out=0 %s twi_sda != 1" %
 355             str(dut.peripheral_side_twi_sda_in))
 356
 357     dut.iocell_side_io1_cell_in_in = 1  # now try setting cell1 to 0
 358     yield Timer(2)
 359
 360     # now we test twi sda again after changing io0, it *still* shouldn't change
 361     if dut.peripheral_side_twi_sda_in != 1:
 362         raise TestFailure(
 363             "iocell_io0=1/mux=0/out=0 %s twi_sda != 1" %
 364             str(dut.peripheral_side_twi_sda_in))
 365
 366     # ok that's probably enough, we could check here that actually gpioa1
 367     # was what got set, or we could flip cell1 mux back to 2
 368     # and set cell0 mux back to 0 but things are probably tested
 369     # enough by now
 370
 371     dut._log.info("Ok!, twi_sda test2 passed")
 372
 373 @cocotb.test()
 374 def pinmux_twi_sda3(dut):
 375     """Test for I2C multi-pin one FN_out (route 2 pins out to same function)
 376     """
 377     yield Timer(2)
 378     # mux selection lines, each input two bit wide
 379     dut.mux_lines_cell1_mux_in = 2
 380     yield Timer(2)
 381     # enable input for mux
 382     dut.EN_mux_lines_cell0_mux = 0
 383     dut.EN_mux_lines_cell1_mux = 1
 384     dut.EN_mux_lines_cell2_mux = 0
 385
 386     # first check the working of twi_sda at cell1
 387
 388     # TWI
 389     yield Timer(2)
 390     # define input variables
 391     dut.peripheral_side_twi_sda_out_in = 0
 392     dut.peripheral_side_twi_sda_outen_in = 1
 393
 394     yield Timer(2)
 395     # the output passed by twi_sda = 0 should be passed
 396     # to io1_cell__out
 397     dut._log.info("io1_out %s" % dut.iocell_side_io1_cell_out)
 398     # Test for out for twi_sda
 399     if dut.iocell_side_io1_cell_out != 0:
 400         raise TestFailure(
 401             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 0" %
 402             str(dut.iocell_side_io1_cell_out))
 403
 404     dut.peripheral_side_twi_sda_out_in = 1
 405     yield Timer(2)
 406     # ok, now io1_cell_out should be equal to 1
 407     if dut.iocell_side_io1_cell_out != 1:
 408         raise TestFailure(
 409             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 410             str(dut.iocell_side_io1_cell_out))
 411
 412     # ok, now let's set the mux lines to cell0
 413     # and select twi_sda : pin 0/mux 3
 414
 415     dut.mux_lines_cell0_mux_in = 3
 416     dut.EN_mux_lines_cell0_mux = 1
 417     yield Timer(2)
 418     # ok, now the output io0_cell_out should be 1 as
 419     # FNout remains is not changed
 420     # this also tests the working of twi_sda at cell0
 421
 422     if dut.iocell_side_io0_cell_out != 1:
 423         raise TestFailure(
 424             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 425             str(dut.iocell_side_io1_cell_out))
 426
 427     # Now, let's test the working of output muxing logic
 428     # at cell 0, by enabling the mux selection line for
 429     # gpio 0. The io0_cell_out should change, but
 430     # twi_sda should remain at value 1
 431     # so set value of gpio0_out_in  = 0
 432
 433     dut.mux_lines_cell0_mux_in = 0
 434     dut.peripheral_side_gpioa_a0_out_in = 0
 435     dut.peripheral_side_gpioa_a0_outen_in = 1
 436
 437     yield Timer(2)
 438     # check the output is correctly getting passed
 439     if dut.iocell_side_io0_cell_out != 0:  # output of iopad
 440         raise TestFailure(
 441             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
 442             str(dut.iocell_side_io2_cell_out))
 443
 444     yield Timer(2)
 445
 446     if dut.peripheral_side_twi_sda_out_in != 1:  # output of twi_sda
 447         raise TestFailure(
 448             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
 449             str(dut.iocell_side_io2_cell_out))
 450
 451     # Now, let's test the working of output muxing logic
 452     # at cell1. First, the output of io1_cell_out should
 453     # be the previous value (1).
 454
 455     yield Timer(2)
 456     if dut.iocell_side_io1_cell_out != 1:
 457         raise TestFailure(
 458             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 459             str(dut.iocell_side_io1_cell_out))
 460
 461     # ok, now set the muxing selection line for gpio1
 462     # again, the value of gpio_out_in should be 0
 463     # ie. opposite of twi_sda_out
 464     dut.mux_lines_cell1_mux_in = 1
 465     dut.peripheral_side_gpioa_a1_out_in = 0
 466     dut.peripheral_side_gpioa_a1_outen_in = 1
 467
 468     yield Timer(2)
 469     if dut.iocell_side_io1_cell_out != 0:
 470         raise TestFailure(
 471             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 472             str(dut.iocell_side_io1_cell_out))
 473
 474     dut._log.info("Ok!, twi_sda test3 passed")