src/test_bsv/tests/test_pinmux.py

   1 # Simple tests for an pinmux module
   2 import cocotb
   3 from cocotb.triggers import Timer
   4 from cocotb.result import TestFailure
   5 #from pinmux_model import pinmux_model
   6 import random
   7
   8
   9 """ dut is design under test """
  10
  11
  12 @cocotb.test()
  13 def pinmux_gpio2(dut):
  14     """Test for GPIO2"""
  15     yield Timer(2)
  16     # mux selection lines, each input two bit wide
  17     dut.mux_lines_cell2_mux_in = 0
  18     yield Timer(2)
  19     # enable input for mux
  20     dut.EN_mux_lines_cell0_mux = 0
  21     dut.EN_mux_lines_cell1_mux = 0
  22     dut.EN_mux_lines_cell2_mux = 1
  23
  24     yield Timer(2)
  25
  26     # GPIO2-out test
  27     # GPIO is inout peripheral
  28     dut.peripheral_side_gpioa_a2_out_in = 0
  29     dut.peripheral_side_gpioa_a2_outen_in = 1
  30
  31     yield Timer(2)
  32
  33     if dut.iocell_side_io2_cell_out != 0:  # output of iopad
  34         raise TestFailure(
  35             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
  36             str(dut.iocell_side_io2_cell_out))
  37
  38     dut.peripheral_side_gpioa_a2_out_in = 1
  39
  40     yield Timer(2)
  41
  42     if dut.iocell_side_io2_cell_out != 1:
  43         raise TestFailure(
  44             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  45             str(dut.iocell_side_io2_cell_out))
  46
  47     # GPIO2-in test (first see if it's tri-state)
  48     if str(dut.peripheral_side_gpioa_a2_in) != "x":
  49         raise TestFailure(
  50             "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
  51             str(dut.peripheral_side_gpioa_a2_in))
  52
  53     dut.peripheral_side_gpioa_a2_outen_in = 0
  54     dut.iocell_side_io2_cell_in_in = 0
  55     yield Timer(2)
  56
  57     if dut.peripheral_side_gpioa_a2_in != 0:
  58         raise TestFailure(
  59             "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
  60             str(dut.peripheral_side_gpioa_a2_in))
  61
  62     dut.iocell_side_io2_cell_in_in = 1
  63     yield Timer(2)
  64
  65     if dut.peripheral_side_gpioa_a2_in != 1:
  66         raise TestFailure(
  67             "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
  68             str(dut.peripheral_side_gpioa_a2_in))
  69
  70     dut.peripheral_side_gpioa_a2_outen_in = 1
  71     dut.iocell_side_io2_cell_in_in = 0
  72     yield Timer(2)
  73     dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_gpioa_a2_in)
  74
  75     if dut.iocell_side_io2_cell_out != 1:
  76         raise TestFailure(
  77             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  78             str(dut.iocell_side_io2_cell_out))
  79
  80     dut._log.info("Ok!")
  81
  82 @cocotb.test()
  83 def pinmux_uart(dut):
  84     """Test for UART"""
  85     yield Timer(2)
  86     # mux selection lines, each input two bit wide
  87     dut.mux_lines_cell0_mux_in = 1
  88     yield Timer(2)
  89     # enable input for mux
  90     dut.EN_mux_lines_cell0_mux = 1
  91     dut.EN_mux_lines_cell1_mux = 0
  92     dut.EN_mux_lines_cell2_mux = 0
  93
  94     yield Timer(2)
  95
  96     # UART
  97     yield Timer(2)
  98     dut.peripheral_side_uart_tx_in = 1
  99     dut.peripheral_side_gpioa_a0_outen_in = 1
 100
 101     yield Timer(2)
 102
 103     if dut.iocell_side_io0_cell_out != 1:
 104         raise TestFailure(
 105             "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
 106             str(dut.iocell_side_io0_cell_out))
 107
 108     dut.peripheral_side_uart_tx_in = 0
 109
 110     yield Timer(2)
 111
 112     if dut.iocell_side_io0_cell_out != 0:
 113         raise TestFailure(
 114             "uart_tx=0/mux=0/out=1 %s iocell_io0 != 0" %
 115             str(dut.iocell_side_io0_cell_out))
 116
 117     dut._log.info("Ok!")
 118
 119 @cocotb.test()
 120 def pinmux_twi_scl(dut):
 121     """Test for I2C SCL"""
 122     yield Timer(2)
 123     # mux selection lines, each input two bit wide
 124     dut.mux_lines_cell0_mux_in = 1
 125     dut.mux_lines_cell1_mux_in = 2
 126     dut.mux_lines_cell2_mux_in = 0
 127     yield Timer(2)
 128     # enable input for mux
 129     dut.EN_mux_lines_cell0_mux = 0
 130     dut.EN_mux_lines_cell1_mux = 1
 131     dut.EN_mux_lines_cell2_mux = 0
 132
 133     yield Timer(2)
 134
 135     # Test for out for twi_scl
 136     dut.peripheral_side_twi_scl_out_in = 0
 137     dut.peripheral_side_twi_scl_outen_in = 1
 138     yield Timer(2)
 139
 140     if dut.iocell_side_io2_cell_out != 0:
 141         raise TestFailure(
 142             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 143             str(dut.iocell_side_io2_cell_out))
 144
 145     dut.peripheral_side_twi_scl_out_in = 1
 146     yield Timer(2)
 147
 148     if dut.iocell_side_io2_cell_out != 1:
 149         raise TestFailure(
 150             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 151             str(dut.iocell_side_io2_cell_out))
 152
 153     # Test for in
 154     # first check for tristate
 155     if str(dut.peripheral_side_twi_scl_in) != "x":
 156         raise TestFailure(
 157             "twi_scl=0/mux=0/out=1 %s twi_scl_in != x" %
 158             str(dut.peripheral_side_twi_scl_in))
 159
 160     dut.peripheral_side_twi_scl_outen_in = 0
 161     dut.iocell_side_io2_cell_in_in = 0
 162     yield Timer(2)
 163
 164     if dut.peripheral_side_twi_scl_in != 0:
 165         raise TestFailure(
 166             "iocell_io2=0/mux=0/out=0 %s twi_scl != 0" %
 167             str(dut.peripheral_side_twi_scl_in))
 168
 169     dut.iocell_side_io2_cell_in_in = 1
 170     yield Timer(2)
 171
 172     if dut.peripheral_side_twi_scl_in != 1:
 173         raise TestFailure(
 174             "iocell_io2=1/mux=0/out=0 %s twi_scl != 1" %
 175             str(dut.peripheral_side_twi_scl_in))
 176
 177     dut.peripheral_side_twi_scl_outen_in = 1
 178     dut.iocell_side_io2_cell_in_in = 0
 179     yield Timer(2)
 180     dut._log.info("twi_scl_in %s" % dut.peripheral_side_twi_scl_in)
 181
 182     if dut.iocell_side_io2_cell_out != 1:
 183         raise TestFailure(
 184             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 1" %
 185             str(dut.iocell_side_io2_cell_out))
 186
 187     yield Timer(2)
 188
 189     dut._log.info("Ok!")
 190
 191 @cocotb.test()
 192 def pinmux_twi_sda(dut):
 193     """Test for I2C"""
 194     yield Timer(2)
 195     # mux selection lines, each input two bit wide
 196     dut.mux_lines_cell1_mux_in = 2
 197     yield Timer(2)
 198     # enable input for mux
 199     dut.EN_mux_lines_cell0_mux = 0
 200     dut.EN_mux_lines_cell1_mux = 1
 201     dut.EN_mux_lines_cell2_mux = 0
 202
 203     yield Timer(2)
 204
 205     # TWI
 206     yield Timer(2)
 207     # define input variables
 208     dut.peripheral_side_twi_sda_out_in = 0
 209     dut.peripheral_side_twi_sda_outen_in = 1
 210
 211     yield Timer(2)
 212
 213     dut._log.info("io1_out %s" % dut.iocell_side_io1_cell_out)
 214     # Test for out for twi_sda
 215     if dut.iocell_side_io1_cell_out != 0:
 216         raise TestFailure(
 217             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 0" %
 218             str(dut.iocell_side_io1_cell_out))
 219
 220     dut.peripheral_side_twi_sda_out_in = 1
 221     yield Timer(2)
 222
 223     if dut.iocell_side_io1_cell_out != 1:
 224         raise TestFailure(
 225             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 226             str(dut.iocell_side_io1_cell_out))
 227
 228     # Test for in
 229     # first check for tristate
 230     if str(dut.peripheral_side_twi_sda_in) != "x":
 231         raise TestFailure(
 232             "twi_sda=0/mux=0/out=1 %s twi_sda_in != x" %
 233             str(dut.peripheral_side_twi_sda_in))
 234
 235     dut.peripheral_side_twi_sda_outen_in = 0
 236     dut.iocell_side_io1_cell_in_in = 0
 237     yield Timer(2)
 238
 239     if dut.peripheral_side_twi_sda_in != 0:
 240         raise TestFailure(
 241             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 242             str(dut.peripheral_side_twi_sda_in))
 243
 244     dut.iocell_side_io1_cell_in_in = 1
 245     yield Timer(2)
 246
 247     if dut.peripheral_side_twi_sda_in != 1:
 248         raise TestFailure(
 249             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 250             str(dut.peripheral_side_twi_sda_in))
 251
 252     dut.peripheral_side_twi_sda_outen_in = 1
 253     dut.iocell_side_io1_cell_in_in = 0
 254     yield Timer(2)
 255     dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
 256
 257     if dut.iocell_side_io1_cell_out != 1:
 258         raise TestFailure(
 259             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 1" %
 260             str(dut.iocell_side_io1_cell_out))
 261
 262     yield Timer(2)
 263