src/test_bsv/tests/test_pinmux.py

   1 # Simple tests for an pinmux module
   2 import cocotb
   3 from cocotb.triggers import Timer
   4 from cocotb.result import TestFailure
   5 #from pinmux_model import pinmux_model
   6 import random
   7
   8
   9 @cocotb.test()
  10 def pinmux_basic_test(dut):
  11     """Test for 5 + 10"""
  12     yield Timer(2)
  13
  14     dut.mux_lines_cell0_mux_in = 1
  15     dut.mux_lines_cell1_mux_in = 2
  16     dut.mux_lines_cell2_mux_in = 0
  17     yield Timer(2)
  18     dut.EN_mux_lines_cell0_mux = 1
  19     dut.EN_mux_lines_cell1_mux = 1
  20     dut.EN_mux_lines_cell2_mux = 1
  21
  22     yield Timer(2)
  23
  24     # GPIO2-out test
  25     dut.peripheral_side_gpioa_a2_out_in = 0
  26     dut.peripheral_side_gpioa_a2_outen_in = 1
  27
  28     yield Timer(2)
  29
  30     if dut.iocell_side_io2_cell_out != 0:
  31         raise TestFailure(
  32             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
  33             str(dut.iocell_side_io2_cell_out))
  34
  35     dut.peripheral_side_gpioa_a2_out_in = 1
  36
  37     yield Timer(2)
  38
  39     if dut.iocell_side_io2_cell_out != 1:
  40         raise TestFailure(
  41             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  42             str(dut.iocell_side_io2_cell_out))
  43
  44     # GPIO2-in test (first see if it's tri-state)
  45     if str(dut.peripheral_side_gpioa_a2_in) != "x":
  46         raise TestFailure(
  47             "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
  48             str(dut.peripheral_side_gpioa_a2_in))
  49
  50     dut.peripheral_side_gpioa_a2_outen_in = 0
  51     dut.iocell_side_io2_cell_in_in = 0
  52     yield Timer(2)
  53
  54     if dut.peripheral_side_gpioa_a2_in != 0:
  55         raise TestFailure(
  56             "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
  57             str(dut.peripheral_side_gpioa_a2_in))
  58
  59     dut.iocell_side_io2_cell_in_in = 1
  60     yield Timer(2)
  61
  62     if dut.peripheral_side_gpioa_a2_in != 1:
  63         raise TestFailure(
  64             "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
  65             str(dut.peripheral_side_gpioa_a2_in))
  66
  67     dut.peripheral_side_gpioa_a2_outen_in = 1
  68     dut.iocell_side_io2_cell_in_in = 0
  69     yield Timer(2)
  70     dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_gpioa_a2_in)
  71
  72     if dut.iocell_side_io2_cell_out != 1:
  73         raise TestFailure(
  74             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  75             str(dut.iocell_side_io2_cell_out))
  76
  77     # UART
  78     yield Timer(2)
  79     dut.peripheral_side_uart_tx_in = 1
  80     dut.peripheral_side_gpioa_a0_outen_in = 1
  81
  82     yield Timer(2)
  83
  84     if dut.iocell_side_io0_cell_out != 1:
  85         raise TestFailure(
  86             "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
  87             str(dut.iocell_side_io0_cell_out))
  88
  89     dut.peripheral_side_uart_tx_in = 0
  90
  91     yield Timer(2)
  92
  93     if dut.iocell_side_io0_cell_out != 0:
  94         raise TestFailure(
  95             "uart_tx=0/mux=0/out=1 %s iocell_io0 != 0" %
  96             str(dut.iocell_side_io0_cell_out))
  97
  98     dut._log.info("Ok!")
  99     yield Timer(2)
 100
 101     # TWI
 102     yield Timer(2)
 103     # define input variables
 104     dut.peripheral_side_twi_sda_out_in = 0
 105     dut.peripheral_side_twi_sda_outen_in = 1
 106     dut.peripheral_side_twi_scl_out_in = 0
 107     dut.peripheral_side_twi_scl_outen_in = 1
 108
 109     yield Timer(2)
 110     #Test for out
 111     if dut.iocell_side_io1_cell_out != 0:
 112         raise TestFailure(
 113             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
 114             str(dut.iocell_side_io1_cell_out))
 115
 116     dut.peripheral_side_twi_sda_out_in = 1
 117
 118     if dut.iocell_side_io1_cell_out != 1:
 119         raise TestFailure(
 120             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
 121             str(dut.iocell_side_io1_cell_out))
 122
 123     # Test for in
 124     # first check for tristate
 125     if str(dut.peripheral_side_twi_sda_in) != "x":
 126         raise TestFailure(
 127             "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
 128             str(dut.peripheral_side_twi_sda_in))
 129
 130     dut.peripheral_side_twi_sda_outen_in = 0
 131     dut.iocell_side_io1_cell_in_in = 0
 132     yield Timer(2)
 133
 134     if dut.peripheral_side_twi_sda_in != 0:
 135         raise TestFailure(
 136             "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
 137             str(dut.peripheral_side_twi_sda_in))
 138
 139     dut.iocell_side_io1_cell_in_in = 1
 140     yield Timer(2)
 141
 142     if dut.peripheral_side_twi_sda_in != 1:
 143         raise TestFailure(
 144             "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
 145             str(dut.peripheral_side_twi_sda_in))
 146
 147     dut.peripheral_side_twi_sda_outen_in = 1
 148     dut.iocell_side_io1_cell_in_in = 0
 149     yield Timer(2)
 150     dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_twi_sda_in)
 151
 152     if dut.iocell_side_io1_cell_out != 1:
 153         raise TestFailure(
 154             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
 155             str(dut.iocell_side_io1_cell_out))
 156
 157     yield Timer(2)
 158
 159 #Test for out
 160     if dut.iocell_side_io2_cell_out != 0:
 161         raise TestFailure(
 162             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
 163             str(dut.iocell_side_io2_cell_out))
 164
 165     dut.peripheral_side_twi_scl_out_in = 1
 166
 167     if dut.iocell_side_io2_cell_out != 1:
 168         raise TestFailure(
 169             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
 170             str(dut.iocell_side_io2_cell_out))
 171
 172     # Test for in
 173     # first check for tristate
 174     if str(dut.peripheral_side_twi_scl_in) != "x":
 175         raise TestFailure(
 176             "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
 177             str(dut.peripheral_side_twi_scl_in))
 178
 179     dut.peripheral_side_twi_scl_outen_in = 0
 180     dut.iocell_side_io2_cell_in_in = 0
 181     yield Timer(2)
 182
 183     if dut.peripheral_side_twi_scl_in != 0:
 184         raise TestFailure(
 185             "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
 186             str(dut.peripheral_side_twi_scl_in))
 187
 188     dut.iocell_side_io2_cell_in_in = 1
 189     yield Timer(2)
 190
 191     if dut.peripheral_side_twi_scl_in != 1:
 192         raise TestFailure(
 193             "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
 194             str(dut.peripheral_side_twi_scl_in))
 195
 196     dut.peripheral_side_twi_scl_outen_in = 1
 197     dut.iocell_side_io2_cell_in_in = 0
 198     yield Timer(2)
 199     dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_twi_scl_in)
 200
 201     if dut.iocell_side_io2_cell_out != 1:
 202         raise TestFailure(
 203             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
 204             str(dut.iocell_side_io2_cell_out))
 205
 206     yield Timer(2)
 207
 208
 209
 210 @cocotb.test()
 211 def pinmux_randomised_test(dut):
 212     """Test for adding 2 random numbers multiple times"""
 213
 214     return
 215
 216     yield Timer(2)
 217
 218     for i in range(10):
 219         A = random.randint(0, 15)
 220         B = random.randint(0, 15)
 221
 222         dut.A = A
 223         dut.B = B
 224
 225         yield Timer(2)
 226
 227         if int(dut.X) != pinmux_model(A, B):
 228             raise TestFailure(
 229                 "Randomised test failed with: %s + %s = %s" %
 230                 (int(dut.A), int(dut.B), int(dut.X)))
 231         else:  # these last two lines are not strictly necessary
 232             dut._log.info("Ok!")