1 from nmigen
import Signal
, Module
, Elaboratable
2 from nmigen
.compat
.sim
import run_simulation
4 # test for https://github.com/nmigen/nmigen/issues/344
7 class MyModule(Elaboratable
):
11 def elaborate(self
, platform
):
13 m
.d
.sync
+= self
.a
.eq(~self
.a
)
25 run_simulation(dut
, generator(),
26 vcd_name
="test_run_simulation_bug.vcd")
29 if __name__
== '__main__':