syscon.vhdl

   1 -- syscon module, a bunch of misc global system control MMIO registers
   2 library ieee;
   3 use ieee.std_logic_1164.all;
   4 use ieee.numeric_std.all;
   5
   6 library work;
   7 use work.wishbone_types.all;
   8
   9 entity syscon is
  10     generic (
  11         SIG_VALUE     : std_ulogic_vector(63 downto 0) := x"f00daa5500010001";
  12         CLK_FREQ      : integer;
  13         HAS_UART      : boolean;
  14         HAS_DRAM      : boolean;
  15         BRAM_SIZE     : integer;
  16         DRAM_SIZE     : integer
  17         );
  18     port (
  19         clk : in std_ulogic;
  20         rst : in std_ulogic;
  21
  22         -- Wishbone ports:
  23         wishbone_in : in wb_io_master_out;
  24         wishbone_out : out wb_io_slave_out;
  25
  26         -- System control ports
  27         dram_at_0  : out std_ulogic;
  28         core_reset : out std_ulogic;
  29         soc_reset  : out std_ulogic
  30         );
  31 end entity syscon;
  32
  33
  34 architecture behaviour of syscon is
  35     -- Register address bits
  36     constant SYS_REG_BITS       : positive := 3;
  37
  38     -- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg)
  39     constant SYS_REG_SIG        : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000";
  40     constant SYS_REG_INFO       : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001";
  41     constant SYS_REG_BRAMINFO   : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "010";
  42     constant SYS_REG_DRAMINFO   : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "011";
  43     constant SYS_REG_CLKINFO    : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "100";
  44     constant SYS_REG_CTRL       : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "101";
  45
  46     -- Muxed reg read signal
  47     signal reg_out      : std_ulogic_vector(63 downto 0);
  48
  49     -- INFO register bits
  50     constant SYS_REG_INFO_HAS_UART    : integer := 0;
  51     constant SYS_REG_INFO_HAS_DRAM    : integer := 1;
  52
  53     -- BRAMINFO contains the BRAM size in the bottom 52 bits
  54     -- DRAMINFO contains the DRAM size if any in the bottom 52 bits
  55     -- (both have reserved top bits for future use)
  56     -- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits
  57
  58     -- CTRL register bits
  59     constant SYS_REG_CTRL_BITS       : positive := 3;
  60     constant SYS_REG_CTRL_DRAM_AT_0  : integer := 0;
  61     constant SYS_REG_CTRL_CORE_RESET : integer := 1;
  62     constant SYS_REG_CTRL_SOC_RESET  : integer := 2;
  63
  64     -- Ctrl register
  65     signal reg_ctrl     : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0);
  66     signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
  67
  68     -- Others
  69     signal reg_info      : std_ulogic_vector(63 downto 0);
  70     signal reg_braminfo  : std_ulogic_vector(63 downto 0);
  71     signal reg_draminfo  : std_ulogic_vector(63 downto 0);
  72     signal reg_clkinfo   : std_ulogic_vector(63 downto 0);
  73     signal info_has_dram : std_ulogic;
  74     signal info_has_uart : std_ulogic;
  75     signal info_clk      : std_ulogic_vector(39 downto 0);
  76 begin
  77
  78     -- Generated output signals
  79     dram_at_0 <= reg_ctrl(SYS_REG_CTRL_DRAM_AT_0);
  80     soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET);
  81     core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET);
  82
  83     -- All register accesses are single cycle
  84     wishbone_out.ack <= wishbone_in.cyc and wishbone_in.stb;
  85     wishbone_out.stall <= '0';
  86
  87     -- Info register is hard wired
  88     info_has_uart <= '1' when HAS_UART else '0';
  89     info_has_dram <= '1' when HAS_DRAM else '0';
  90     info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40));
  91     reg_info <= (0 => info_has_uart,
  92                  1 => info_has_dram,
  93                  others => '0');
  94     reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52));
  95     reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM
  96                     else (others => '0');
  97     reg_clkinfo <= (39 downto 0 => info_clk,
  98                     others => '0');
  99
 100     -- Control register read composition
 101     reg_ctrl_out <= (63 downto SYS_REG_CTRL_BITS => '0',
 102                     SYS_REG_CTRL_BITS-1 downto 0 => reg_ctrl);
 103
 104     -- Register read mux
 105     with wishbone_in.adr(SYS_REG_BITS+2 downto 3) select reg_out <=
 106         SIG_VALUE       when SYS_REG_SIG,
 107         reg_info        when SYS_REG_INFO,
 108         reg_braminfo    when SYS_REG_BRAMINFO,
 109         reg_draminfo    when SYS_REG_DRAMINFO,
 110         reg_clkinfo     when SYS_REG_CLKINFO,
 111         reg_ctrl_out    when SYS_REG_CTRL,
 112         (others => '0') when others;
 113     wishbone_out.dat <= reg_out(63 downto 32) when wishbone_in.adr(2) = '1' else
 114                         reg_out(31 downto 0);
 115
 116     -- Register writes
 117     regs_write: process(clk)
 118     begin
 119         if rising_edge(clk) then
 120             if (rst) then
 121                 reg_ctrl <= (others => '0');
 122             else
 123                 if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then
 124                     -- Change this if CTRL ever has more than 32 bits
 125                     if wishbone_in.adr(SYS_REG_BITS+2 downto 3) = SYS_REG_CTRL and
 126                         wishbone_in.adr(2) = '0' then
 127                         reg_ctrl(SYS_REG_CTRL_BITS-1 downto 0) <=
 128                             wishbone_in.dat(SYS_REG_CTRL_BITS-1 downto 0);
 129                     end if;
 130                 end if;
 131
 132                 -- Reset auto-clear
 133                 if reg_ctrl(SYS_REG_CTRL_SOC_RESET) = '1' then
 134                     reg_ctrl(SYS_REG_CTRL_SOC_RESET) <= '0';
 135                 end if;
 136                 if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then
 137                     reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0';
 138                 end if;
 139             end if;
 140         end if;
 141     end process;
 142
 143 end architecture behaviour;