syscon.vhdl

   1 -- syscon module, a bunch of misc global system control MMIO registers
   2 library ieee;
   3 use ieee.std_logic_1164.all;
   4 use ieee.numeric_std.all;
   5
   6 library work;
   7 use work.wishbone_types.all;
   8
   9 entity syscon is
  10     generic (
  11         SIG_VALUE        : std_ulogic_vector(63 downto 0) := x"f00daa5500010001";
  12         CLK_FREQ         : integer;
  13         HAS_UART         : boolean;
  14         HAS_DRAM         : boolean;
  15         BRAM_SIZE        : integer;
  16         DRAM_SIZE        : integer;
  17         DRAM_INIT_SIZE   : integer;
  18         HAS_SPI_FLASH    : boolean;
  19         SPI_FLASH_OFFSET : integer;
  20         HAS_LITEETH      : boolean;
  21         UART0_IS_16550   : boolean;
  22         HAS_UART1        : boolean
  23         );
  24     port (
  25         clk : in std_ulogic;
  26         rst : in std_ulogic;
  27
  28         -- Wishbone ports:
  29         wishbone_in : in wb_io_master_out;
  30         wishbone_out : out wb_io_slave_out;
  31
  32         -- System control ports
  33         dram_at_0  : out std_ulogic;
  34         core_reset : out std_ulogic;
  35         soc_reset  : out std_ulogic
  36         );
  37 end entity syscon;
  38
  39
  40 architecture behaviour of syscon is
  41     -- Register address bits
  42     constant SYS_REG_BITS       : positive := 6;
  43
  44     -- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg)
  45     constant SYS_REG_SIG          : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000000";
  46     constant SYS_REG_INFO         : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000001";
  47     constant SYS_REG_BRAMINFO     : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000010";
  48     constant SYS_REG_DRAMINFO     : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000011";
  49     constant SYS_REG_CLKINFO      : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000100";
  50     constant SYS_REG_CTRL         : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000101";
  51     constant SYS_REG_DRAMINITINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000110";
  52     constant SYS_REG_SPIFLASHINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000111";
  53     constant SYS_REG_UART0_INFO   : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001000";
  54     constant SYS_REG_UART1_INFO   : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001001";
  55
  56     -- Muxed reg read signal
  57     signal reg_out      : std_ulogic_vector(63 downto 0);
  58
  59     -- INFO register bits
  60     constant SYS_REG_INFO_HAS_UART    : integer := 0;  -- Has a UART (always set)
  61     constant SYS_REG_INFO_HAS_DRAM    : integer := 1;  -- Has DRAM
  62     constant SYS_REG_INFO_HAS_BRAM    : integer := 2;  -- Has "main" BRAM
  63     constant SYS_REG_INFO_HAS_SPIF    : integer := 3;  -- Has SPI flash
  64     constant SYS_REG_INFO_HAS_LETH    : integer := 4;  -- Has LiteEth ethernet
  65     constant SYS_REG_INFO_HAS_LSYS    : integer := 5;  -- Has 6-bit address syscon
  66     constant SYS_REG_INFO_HAS_URT1    : integer := 6;  -- Has second UART
  67
  68     -- BRAMINFO contains the BRAM size in the bottom 52 bits
  69     -- DRAMINFO contains the DRAM size if any in the bottom 52 bits
  70     -- (both have reserved top bits for future use)
  71     -- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits
  72
  73     -- CTRL register bits
  74     constant SYS_REG_CTRL_BITS       : positive := 3;
  75     constant SYS_REG_CTRL_DRAM_AT_0  : integer := 0;
  76     constant SYS_REG_CTRL_CORE_RESET : integer := 1;
  77     constant SYS_REG_CTRL_SOC_RESET  : integer := 2;
  78
  79     -- SPI Info register bits
  80     --
  81     -- Top 32-bit is flash offset which is the amount of flash
  82     -- reserved for the FPGA bitfile if any
  83     constant SYS_REG_SPI_INFO_IS_FLASH : integer := 0;
  84
  85     -- UART0/1 info registers bits
  86     --
  87     --  0 ..31  : UART clock freq (in HZ)
  88     --      32  : UART is 16550 (otherwise pp)
  89     --
  90
  91     -- Ctrl register
  92     signal reg_ctrl     : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0);
  93     signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
  94
  95     -- Others
  96     signal reg_info      : std_ulogic_vector(63 downto 0);
  97     signal reg_braminfo  : std_ulogic_vector(63 downto 0);
  98     signal reg_draminfo  : std_ulogic_vector(63 downto 0);
  99     signal reg_dramiinfo : std_ulogic_vector(63 downto 0);
 100     signal reg_clkinfo   : std_ulogic_vector(63 downto 0);
 101     signal reg_spiinfo   : std_ulogic_vector(63 downto 0);
 102     signal reg_uart0info : std_ulogic_vector(63 downto 0);
 103     signal reg_uart1info : std_ulogic_vector(63 downto 0);
 104     signal info_has_dram : std_ulogic;
 105     signal info_has_bram : std_ulogic;
 106     signal info_has_uart : std_ulogic;
 107     signal info_has_spif : std_ulogic;
 108     signal info_has_leth : std_ulogic;
 109     signal info_has_urt1 : std_ulogic;
 110     signal info_clk      : std_ulogic_vector(39 downto 0);
 111     signal info_fl_off   : std_ulogic_vector(31 downto 0);
 112     signal uinfo_16550   : std_ulogic;
 113     signal uinfo_freq    : std_ulogic_vector(31 downto 0);
 114
 115     -- Wishbone response latch
 116     signal wb_rsp        : wb_io_slave_out;
 117 begin
 118
 119     -- Generated output signals
 120     dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0);
 121     soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET);
 122     core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET);
 123
 124     -- Info register is hard wired
 125     info_has_uart <= '1' when HAS_UART       else '0';
 126     info_has_dram <= '1' when HAS_DRAM       else '0';
 127     info_has_bram <= '1' when BRAM_SIZE /= 0 else '0';
 128     info_has_spif <= '1' when HAS_SPI_FLASH  else '0';
 129     info_has_leth <= '1' when HAS_LITEETH    else '0';
 130     info_has_urt1 <= '1' when HAS_UART1      else '0';
 131     info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40));
 132     reg_info <= (SYS_REG_INFO_HAS_UART  => info_has_uart,
 133                  SYS_REG_INFO_HAS_DRAM  => info_has_dram,
 134                  SYS_REG_INFO_HAS_BRAM  => info_has_bram,
 135                  SYS_REG_INFO_HAS_SPIF  => info_has_spif,
 136                  SYS_REG_INFO_HAS_LETH  => info_has_leth,
 137                  SYS_REG_INFO_HAS_LSYS  => '1',
 138                  SYS_REG_INFO_HAS_URT1  => info_has_urt1,
 139                  others => '0');
 140
 141     reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52));
 142     reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM
 143                     else (others => '0');
 144     reg_dramiinfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_INIT_SIZE, 52)) when HAS_DRAM
 145                      else (others => '0');
 146     reg_clkinfo <= (39 downto 0 => info_clk,
 147                     others => '0');
 148     info_fl_off <= std_ulogic_vector(to_unsigned(SPI_FLASH_OFFSET, 32));
 149     reg_spiinfo <= (31 downto 0 => info_fl_off,
 150                     others => '0');
 151
 152     -- Control register read composition
 153     reg_ctrl_out <= (63 downto SYS_REG_CTRL_BITS => '0',
 154                     SYS_REG_CTRL_BITS-1 downto 0 => reg_ctrl);
 155
 156     -- UART info registers read composition
 157     uinfo_16550   <= '1' when UART0_IS_16550 else '0';
 158     uinfo_freq    <= std_ulogic_vector(to_unsigned(CLK_FREQ, 32));
 159     reg_uart0info <= (32           => uinfo_16550,
 160                       31 downto 0  => uinfo_freq,
 161                       others       => '0');
 162     reg_uart1info <= (32           => '1',
 163                       31 downto 0  => uinfo_freq,
 164                       others       => '0');
 165
 166     -- Wishbone response
 167     wb_rsp.ack <= wishbone_in.cyc and wishbone_in.stb;
 168     with wishbone_in.adr(SYS_REG_BITS+2 downto 3) select reg_out <=
 169         SIG_VALUE       when SYS_REG_SIG,
 170         reg_info        when SYS_REG_INFO,
 171         reg_braminfo    when SYS_REG_BRAMINFO,
 172         reg_draminfo    when SYS_REG_DRAMINFO,
 173         reg_dramiinfo   when SYS_REG_DRAMINITINFO,
 174         reg_clkinfo     when SYS_REG_CLKINFO,
 175         reg_ctrl_out    when SYS_REG_CTRL,
 176         reg_spiinfo     when SYS_REG_SPIFLASHINFO,
 177         reg_uart0info   when SYS_REG_UART0_INFO,
 178         reg_uart1info   when SYS_REG_UART1_INFO,
 179         (others => '0') when others;
 180     wb_rsp.dat   <= reg_out(63 downto 32) when wishbone_in.adr(2) = '1' else
 181                   reg_out(31 downto 0);
 182     wb_rsp.stall <= '0';
 183
 184     -- Wishbone response latch
 185     regs_read: process(clk)
 186     begin
 187         if rising_edge(clk) then
 188             -- Send response from latch
 189             wishbone_out <= wb_rsp;
 190         end if;
 191     end process;
 192
 193     -- Register writes
 194     regs_write: process(clk)
 195     begin
 196         if rising_edge(clk) then
 197             if (rst) then
 198                 reg_ctrl <= (others => '0');
 199             else
 200                 if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then
 201                     -- Change this if CTRL ever has more than 32 bits
 202                     if wishbone_in.adr(SYS_REG_BITS+2 downto 3) = SYS_REG_CTRL and
 203                         wishbone_in.adr(2) = '0' then
 204                         reg_ctrl(SYS_REG_CTRL_BITS-1 downto 0) <=
 205                             wishbone_in.dat(SYS_REG_CTRL_BITS-1 downto 0);
 206                     end if;
 207                 end if;
 208
 209                 -- Reset auto-clear
 210                 if reg_ctrl(SYS_REG_CTRL_SOC_RESET) = '1' then
 211                     reg_ctrl(SYS_REG_CTRL_SOC_RESET) <= '0';
 212                 end if;
 213                 if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then
 214                     reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0';
 215                 end if;
 216
 217                 -- If BRAM doesn't exist, force DRAM at 0
 218                 if BRAM_SIZE = 0 then
 219                     reg_ctrl(SYS_REG_CTRL_DRAM_AT_0) <= '1';
 220                 end if;
 221             end if;
 222         end if;
 223     end process;
 224
 225 end architecture behaviour;