syscon.vhdl

   1 -- syscon module, a bunch of misc global system control MMIO registers
   2 library ieee;
   3 use ieee.std_logic_1164.all;
   4 use ieee.numeric_std.all;
   5
   6 library work;
   7 use work.wishbone_types.all;
   8
   9 entity syscon is
  10     generic (
  11         SIG_VALUE        : std_ulogic_vector(63 downto 0) := x"f00daa5500010001";
  12         CLK_FREQ         : integer;
  13         HAS_UART         : boolean;
  14         HAS_DRAM         : boolean;
  15         BRAM_SIZE        : integer;
  16         DRAM_SIZE        : integer;
  17         DRAM_INIT_SIZE   : integer;
  18         HAS_SPI_FLASH    : boolean;
  19         SPI_FLASH_OFFSET : integer
  20         );
  21     port (
  22         clk : in std_ulogic;
  23         rst : in std_ulogic;
  24
  25         -- Wishbone ports:
  26         wishbone_in : in wb_io_master_out;
  27         wishbone_out : out wb_io_slave_out;
  28
  29         -- System control ports
  30         dram_at_0  : out std_ulogic;
  31         core_reset : out std_ulogic;
  32         soc_reset  : out std_ulogic
  33         );
  34 end entity syscon;
  35
  36
  37 architecture behaviour of syscon is
  38     -- Register address bits
  39     constant SYS_REG_BITS       : positive := 3;
  40
  41     -- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg)
  42     constant SYS_REG_SIG          : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000";
  43     constant SYS_REG_INFO         : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001";
  44     constant SYS_REG_BRAMINFO     : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "010";
  45     constant SYS_REG_DRAMINFO     : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "011";
  46     constant SYS_REG_CLKINFO      : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "100";
  47     constant SYS_REG_CTRL         : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "101";
  48     constant SYS_REG_DRAMINITINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "110";
  49     constant SYS_REG_SPIFLASHINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "111";
  50
  51     -- Muxed reg read signal
  52     signal reg_out      : std_ulogic_vector(63 downto 0);
  53
  54     -- INFO register bits
  55     constant SYS_REG_INFO_HAS_UART    : integer := 0;
  56     constant SYS_REG_INFO_HAS_DRAM    : integer := 1;
  57     constant SYS_REG_INFO_HAS_BRAM    : integer := 2;
  58     constant SYS_REG_INFO_HAS_SPIF    : integer := 3;
  59
  60     -- BRAMINFO contains the BRAM size in the bottom 52 bits
  61     -- DRAMINFO contains the DRAM size if any in the bottom 52 bits
  62     -- (both have reserved top bits for future use)
  63     -- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits
  64
  65     -- CTRL register bits
  66     constant SYS_REG_CTRL_BITS       : positive := 3;
  67     constant SYS_REG_CTRL_DRAM_AT_0  : integer := 0;
  68     constant SYS_REG_CTRL_CORE_RESET : integer := 1;
  69     constant SYS_REG_CTRL_SOC_RESET  : integer := 2;
  70
  71     -- SPI Info register bits
  72     --
  73     -- Top 32-bit is flash offset which is the amount of flash
  74     -- reserved for the FPGA bitfile if any
  75     constant SYS_REG_SPI_INFO_IS_FLASH : integer := 0;
  76
  77     -- Ctrl register
  78     signal reg_ctrl     : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0);
  79     signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
  80
  81     -- Others
  82     signal reg_info      : std_ulogic_vector(63 downto 0);
  83     signal reg_braminfo  : std_ulogic_vector(63 downto 0);
  84     signal reg_draminfo  : std_ulogic_vector(63 downto 0);
  85     signal reg_dramiinfo : std_ulogic_vector(63 downto 0);
  86     signal reg_clkinfo   : std_ulogic_vector(63 downto 0);
  87     signal reg_spiinfo   : std_ulogic_vector(63 downto 0);
  88     signal info_has_dram : std_ulogic;
  89     signal info_has_bram : std_ulogic;
  90     signal info_has_uart : std_ulogic;
  91     signal info_has_spif : std_ulogic;
  92     signal info_clk      : std_ulogic_vector(39 downto 0);
  93     signal info_fl_off   : std_ulogic_vector(31 downto 0);
  94 begin
  95
  96     -- Generated output signals
  97     dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0);
  98     soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET);
  99     core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET);
 100
 101     -- All register accesses are single cycle
 102     wishbone_out.ack <= wishbone_in.cyc and wishbone_in.stb;
 103     wishbone_out.stall <= '0';
 104
 105     -- Info register is hard wired
 106     info_has_uart <= '1' when HAS_UART else '0';
 107     info_has_dram <= '1' when HAS_DRAM else '0';
 108     info_has_bram <= '1' when BRAM_SIZE /= 0 else '0';
 109     info_has_spif <= '1' when HAS_SPI_FLASH else '0';
 110     info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40));
 111     reg_info <= (SYS_REG_INFO_HAS_UART  => info_has_uart,
 112                  SYS_REG_INFO_HAS_DRAM  => info_has_dram,
 113                  SYS_REG_INFO_HAS_BRAM  => info_has_bram,
 114                  SYS_REG_INFO_HAS_SPIF  => info_has_spif,
 115                  others => '0');
 116     reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52));
 117     reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM
 118                     else (others => '0');
 119     reg_dramiinfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_INIT_SIZE, 52)) when HAS_DRAM
 120                      else (others => '0');
 121     reg_clkinfo <= (39 downto 0 => info_clk,
 122                     others => '0');
 123     info_fl_off <= std_ulogic_vector(to_unsigned(SPI_FLASH_OFFSET, 32));
 124     reg_spiinfo <= (31 downto 0 => info_fl_off,
 125                     others => '0');
 126
 127     -- Control register read composition
 128     reg_ctrl_out <= (63 downto SYS_REG_CTRL_BITS => '0',
 129                     SYS_REG_CTRL_BITS-1 downto 0 => reg_ctrl);
 130
 131     -- Register read mux
 132     with wishbone_in.adr(SYS_REG_BITS+2 downto 3) select reg_out <=
 133         SIG_VALUE       when SYS_REG_SIG,
 134         reg_info        when SYS_REG_INFO,
 135         reg_braminfo    when SYS_REG_BRAMINFO,
 136         reg_draminfo    when SYS_REG_DRAMINFO,
 137         reg_dramiinfo   when SYS_REG_DRAMINITINFO,
 138         reg_clkinfo     when SYS_REG_CLKINFO,
 139         reg_ctrl_out    when SYS_REG_CTRL,
 140         reg_spiinfo     when SYS_REG_SPIFLASHINFO,
 141         (others => '0') when others;
 142     wishbone_out.dat <= reg_out(63 downto 32) when wishbone_in.adr(2) = '1' else
 143                         reg_out(31 downto 0);
 144
 145     -- Register writes
 146     regs_write: process(clk)
 147     begin
 148         if rising_edge(clk) then
 149             if (rst) then
 150                 reg_ctrl <= (others => '0');
 151             else
 152                 if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then
 153                     -- Change this if CTRL ever has more than 32 bits
 154                     if wishbone_in.adr(SYS_REG_BITS+2 downto 3) = SYS_REG_CTRL and
 155                         wishbone_in.adr(2) = '0' then
 156                         reg_ctrl(SYS_REG_CTRL_BITS-1 downto 0) <=
 157                             wishbone_in.dat(SYS_REG_CTRL_BITS-1 downto 0);
 158                     end if;
 159                 end if;
 160
 161                 -- Reset auto-clear
 162                 if reg_ctrl(SYS_REG_CTRL_SOC_RESET) = '1' then
 163                     reg_ctrl(SYS_REG_CTRL_SOC_RESET) <= '0';
 164                 end if;
 165                 if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then
 166                     reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0';
 167                 end if;
 168
 169                 -- If BRAM doesn't exist, force DRAM at 0
 170                 if BRAM_SIZE = 0 then
 171                     reg_ctrl(SYS_REG_CTRL_DRAM_AT_0) <= '1';
 172                 end if;
 173             end if;
 174         end if;
 175     end process;
 176
 177 end architecture behaviour;