sysdeps/sparc/sparc64/multiarch/memset-niagara4.S

   1 /* Set a block of memory to some byte value.  For SUN4V Niagara-4.
   2    Copyright (C) 2012-2022 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, see
  17    <https://www.gnu.org/licenses/>.  */
  18
  19 #include <sysdep.h>
  20
  21 #define ASI_BLK_INIT_QUAD_LDD_P 0xe2
  22
  23 #if IS_IN (libc)
  24
  25         .register       %g2, #scratch
  26         .register       %g3, #scratch
  27
  28         .text
  29         .align          32
  30
  31 ENTRY(__memset_niagara4)
  32         andcc           %o1, 0xff, %o4
  33         be,pt           %icc, 1f
  34          mov            %o2, %o1
  35         sllx            %o4, 8, %g1
  36         or              %g1, %o4, %o2
  37         sllx            %o2, 16, %g1
  38         or              %g1, %o2, %o2
  39         sllx            %o2, 32, %g1
  40         ba,pt           %icc, 1f
  41          or             %g1, %o2, %o4
  42         clr             %o4
  43 1:      cmp             %o1, 16
  44         ble             %icc, .Ltiny
  45          mov            %o0, %o3
  46         sub             %g0, %o0, %g1
  47         and             %g1, 0x7, %g1
  48         brz,pt          %g1, .Laligned8
  49          sub            %o1, %g1, %o1
  50 1:      stb             %o4, [%o0 + 0x00]
  51         subcc           %g1, 1, %g1
  52         bne,pt          %icc, 1b
  53          add            %o0, 1, %o0
  54 .Laligned8:
  55         cmp             %o1, 64 + (64 - 8)
  56         ble             .Lmedium
  57          sub            %g0, %o0, %g1
  58         andcc           %g1, (64 - 1), %g1
  59         brz,pn          %g1, .Laligned64
  60          sub            %o1, %g1, %o1
  61 1:      stx             %o4, [%o0 + 0x00]
  62         subcc           %g1, 8, %g1
  63         bne,pt          %icc, 1b
  64          add            %o0, 0x8, %o0
  65 .Laligned64:
  66         andn            %o1, 64 - 1, %g1
  67         sub             %o1, %g1, %o1
  68         brnz,pn         %o4, .Lnon_bzero_loop
  69          mov            0x20, %g2
  70 1:      stxa            %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
  71         subcc           %g1, 0x40, %g1
  72         stxa            %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
  73         bne,pt          %icc, 1b
  74          add            %o0, 0x40, %o0
  75 .Lpostloop:
  76         cmp             %o1, 8
  77         bl,pn           %icc, .Ltiny
  78          membar         #StoreStore|#StoreLoad
  79 .Lmedium:
  80         andn            %o1, 0x7, %g1
  81         sub             %o1, %g1, %o1
  82 1:      stx             %o4, [%o0 + 0x00]
  83         subcc           %g1, 0x8, %g1
  84         bne,pt          %icc, 1b
  85          add            %o0, 0x08, %o0
  86         andcc           %o1, 0x4, %g1
  87         be,pt           %icc, .Ltiny
  88          sub            %o1, %g1, %o1
  89         stw             %o4, [%o0 + 0x00]
  90         add             %o0, 0x4, %o0
  91 .Ltiny:
  92         cmp             %o1, 0
  93         be,pn           %icc, .Lexit
  94 1:       subcc          %o1, 1, %o1
  95         stb             %o4, [%o0 + 0x00]
  96         bne,pt          %icc, 1b
  97          add            %o0, 1, %o0
  98 .Lexit:
  99         retl
 100          mov            %o3, %o0
 101 .Lnon_bzero_loop:
 102         mov             0x08, %g3
 103         mov             0x28, %o5
 104 1:      stxa            %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
 105         subcc           %g1, 0x40, %g1
 106         stxa            %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
 107         stxa            %o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
 108         stxa            %o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P
 109         add             %o0, 0x10, %o0
 110         stxa            %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
 111         stxa            %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
 112         stxa            %o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
 113         stxa            %o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P
 114         bne,pt          %icc, 1b
 115          add            %o0, 0x30, %o0
 116         ba,a,pt         %icc, .Lpostloop
 117 END(__memset_niagara4)
 118
 119 #endif