test/test_clock.py

   1 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 import unittest
   5
   6 from litex.soc.cores.clock import *
   7
   8
   9 class TestClock(unittest.TestCase):
  10     # Xilinx / Spartan 6
  11     def test_s6pll(self):
  12         pll = S6PLL()
  13         pll.register_clkin(Signal(), 100e6)
  14         for i in range(pll.nclkouts_max):
  15             pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
  16         pll.compute_config()
  17
  18     def test_s6dcm(self):
  19         dcm = S6DCM()
  20         dcm.register_clkin(Signal(), 100e6)
  21         for i in range(dcm.nclkouts_max):
  22             dcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
  23         dcm.compute_config()
  24
  25     # Xilinx / 7-Series
  26     def test_s7pll(self):
  27         pll = S7PLL()
  28         pll.register_clkin(Signal(), 100e6)
  29         for i in range(pll.nclkouts_max):
  30             pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
  31         pll.compute_config()
  32
  33     def test_s7mmcm(self):
  34         mmcm = S7MMCM()
  35         mmcm.register_clkin(Signal(), 100e6)
  36         for i in range(mmcm.nclkouts_max):
  37             mmcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
  38         mmcm.compute_config()
  39
  40     # Xilinx / Ultrascale
  41     def test_uspll(self):
  42         pll = USPLL()
  43         pll.register_clkin(Signal(), 100e6)
  44         for i in range(pll.nclkouts_max):
  45             pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
  46         pll.compute_config()
  47
  48     def test_usmmcm(self):
  49         mmcm = USMMCM()
  50         mmcm.register_clkin(Signal(), 100e6)
  51         for i in range(mmcm.nclkouts_max):
  52             mmcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
  53         mmcm.compute_config()
  54
  55     # Lattice / iCE40
  56     def test_ice40pll(self):
  57         pll = USMMCM()
  58         pll.register_clkin(Signal(), 100e6)
  59         for i in range(pll.nclkouts_max):
  60             pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
  61         pll.compute_config()
  62
  63     # Lattice / ECP5
  64     def test_ecp5pll(self):
  65         pll = ECP5PLL()
  66         pll.register_clkin(Signal(), 100e6)
  67         for i in range(pll.nclkouts_max):
  68             pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
  69         pll.compute_config()
  70
  71     # Altera / CycloneIV
  72     def test_cycloneivpll(self):
  73         pll = CycloneIVPLL()
  74         pll.register_clkin(Signal(), 50e6)
  75         for i in range(pll.nclkouts_max):
  76             pll.create_clkout(ClockDomain("clkout{}".format(i)), 100e6)
  77         pll.compute_config()
  78
  79     # Altera / CycloneV
  80     def test_cyclonevpll(self):
  81         pll = CycloneVPLL()
  82         pll.register_clkin(Signal(), 50e6)
  83         for i in range(pll.nclkouts_max):
  84             pll.create_clkout(ClockDomain("clkout{}".format(i)), 100e6)
  85         pll.compute_config()