tests/memory.sv

   1 module testbench (
   2   input clk, wen,
   3   input [9:0] addr,
   4   input [7:0] wdata,
   5   output [7:0] rdata
   6 );
   7   memory uut (
   8     .clk  (clk  ),
   9     .wen  (wen  ),
  10     .addr (addr ),
  11     .wdata(wdata),
  12     .rdata(rdata)
  13   );
  14
  15   (* anyconst *) reg [9:0] test_addr;
  16   reg test_data_valid = 0;
  17   reg [7:0] test_data;
  18
  19   always @(posedge clk) begin
  20     if (addr == test_addr) begin
  21       if (wen) begin
  22         test_data <= wdata;
  23         test_data_valid <= 1;
  24       end
  25       if (test_data_valid) begin
  26         assert(test_data == rdata);
  27       end
  28     end
  29   end
  30 endmodule
  31
  32 module memory (
  33   input clk, wen,
  34   input [9:0] addr,
  35   input [7:0] wdata,
  36   output [7:0] rdata
  37 );
  38   reg [7:0] bank0 [0:255];
  39   reg [7:0] bank1 [0:255];
  40   reg [7:0] bank2 [0:255];
  41   reg [7:0] bank3 [0:255];
  42
  43   wire [1:0] mem_sel = addr[9:8];
  44   wire [7:0] mem_addr = addr[7:0];
  45
  46   always @(posedge clk) begin
  47     case (mem_sel)
  48       0: if (wen) bank0[mem_addr] <= wdata;
  49       1: if (wen) bank1[mem_addr] <= wdata;
  50       2: if (wen) bank1[mem_addr] <= wdata;  // BUG: Should assign to bank2
  51       3: if (wen) bank3[mem_addr] <= wdata;
  52     endcase
  53   end
  54
  55   assign rdata =
  56     mem_sel == 0 ? bank0[mem_addr] :
  57     mem_sel == 1 ? bank1[mem_addr] :
  58     mem_sel == 2 ? bank2[mem_addr] :
  59     mem_sel == 3 ? bank3[mem_addr] : 'bx;
  60 endmodule