tests/sva/sva_value_change_sim.sv

   1 module top (
   2         input clk
   3 );
   4
   5 reg [7:0] counter = 0;
   6
   7 reg a = 0;
   8 reg b = 1;
   9 reg c;
  10
  11 wire a_fell; assign a_fell = $fell(a, @(posedge clk));
  12 wire a_rose; assign a_rose = $rose(a, @(posedge clk));
  13 wire a_stable; assign a_stable = $stable(a, @(posedge clk));
  14
  15 wire b_fell; assign b_fell = $fell(b, @(posedge clk));
  16 wire b_rose; assign b_rose = $rose(b, @(posedge clk));
  17 wire b_stable; assign b_stable = $stable(b, @(posedge clk));
  18
  19 wire c_fell; assign c_fell = $fell(c, @(posedge clk));
  20 wire c_rose; assign c_rose = $rose(c, @(posedge clk));
  21 wire c_stable; assign c_stable = $stable(c, @(posedge clk));
  22
  23 always @(posedge clk) begin
  24         counter <= counter + 1;
  25
  26         case (counter)
  27                 0: begin
  28             assert property ( $fell(a) && !$rose(a) && !$stable(a));
  29             assert property (!$fell(b) &&  $rose(b) && !$stable(b));
  30             assert property (!$fell(c) && !$rose(c) &&  $stable(c));
  31             a <= 1; b <= 1; c <= 1;
  32         end
  33                 1: begin a <= 0; b <= 1; c <= 'x; end
  34                 2: begin
  35             assert property ( $fell(a) && !$rose(a) && !$stable(a));
  36             assert property (!$fell(b) && !$rose(b) &&  $stable(b));
  37             assert property (!$fell(c) && !$rose(c) && !$stable(c));
  38             a <= 0; b <= 0; c <= 0;
  39         end
  40                 3: begin a <= 0; b <= 1; c <= 'x; end
  41                 4: begin
  42             assert property (!$fell(a) && !$rose(a) &&  $stable(a));
  43             assert property (!$fell(b) &&  $rose(b) && !$stable(b));
  44             assert property (!$fell(c) && !$rose(c) && !$stable(c));
  45             a <= 'x; b <= 'x; c <= 'x;
  46         end
  47                 5: begin a <= 0; b <= 1; c <= 'x; counter <= 0; end
  48         endcase;
  49 end
  50
  51 endmodule