wishbone_types.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 package wishbone_types is
   5     constant wishbone_addr_bits : integer := 32;
   6     constant wishbone_data_bits : integer := 64;
   7     constant wishbone_sel_bits : integer := wishbone_data_bits/8;
   8
   9     subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
  10     subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
  11     subtype wishbone_sel_type  is std_ulogic_vector(wishbone_sel_bits-1  downto 0);
  12
  13     type wishbone_master_out is record
  14         adr : wishbone_addr_type;
  15         dat : wishbone_data_type;
  16         cyc : std_ulogic;
  17         stb : std_ulogic;
  18         sel : wishbone_sel_type;
  19         we  : std_ulogic;
  20     end record;
  21     constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');
  22
  23     type wishbone_slave_out is record
  24         dat   : wishbone_data_type;
  25         ack   : std_ulogic;
  26         stall : std_ulogic;
  27     end record;
  28     constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', stall => '0', others => (others => '0'));
  29
  30     type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;
  31     type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;
  32
  33 end package wishbone_types;