wishbone_types.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 package wishbone_types is
   5     constant wishbone_addr_bits : integer := 64;
   6     constant wishbone_data_bits : integer := 64;
   7
   8     subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
   9     subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
  10
  11     type wishbone_master_out is record
  12         adr : wishbone_addr_type;
  13         dat : wishbone_data_type;
  14         cyc : std_ulogic;
  15         stb : std_ulogic;
  16         sel : std_ulogic_vector(7 downto 0);
  17         we  : std_ulogic;
  18     end record;
  19     constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0'));
  20
  21     type wishbone_slave_out is record
  22         dat : wishbone_data_type;
  23         ack : std_ulogic;
  24     end record;
  25     constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0'));
  26
  27 end package wishbone_types;