writeback.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.crhelpers.all;
   8
   9 entity writeback is
  10     port (
  11         clk          : in std_ulogic;
  12
  13         e_in         : in Execute1ToWritebackType;
  14         l_in         : in Loadstore1ToWritebackType;
  15
  16         w_out        : out WritebackToRegisterFileType;
  17         c_out        : out WritebackToCrFileType;
  18
  19         complete_out : out std_ulogic
  20         );
  21 end entity writeback;
  22
  23 architecture behaviour of writeback is
  24 begin
  25     writeback_0: process(clk)
  26         variable x : std_ulogic_vector(0 downto 0);
  27         variable y : std_ulogic_vector(0 downto 0);
  28         variable w : std_ulogic_vector(0 downto 0);
  29     begin
  30         if rising_edge(clk) then
  31             -- Do consistency checks only on the clock edge
  32             x(0) := e_in.valid;
  33             y(0) := l_in.valid;
  34             assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
  35
  36             x(0) := e_in.write_enable or e_in.exc_write_enable;
  37             y(0) := l_in.write_enable;
  38             assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
  39
  40             w(0) := e_in.write_cr_enable;
  41             x(0) := (e_in.write_enable and e_in.rc);
  42             assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure;
  43         end if;
  44     end process;
  45
  46     writeback_1: process(all)
  47         variable cf: std_ulogic_vector(3 downto 0);
  48         variable zero : std_ulogic;
  49         variable sign : std_ulogic;
  50         variable scf  : std_ulogic_vector(3 downto 0);
  51     begin
  52         w_out <= WritebackToRegisterFileInit;
  53         c_out <= WritebackToCrFileInit;
  54
  55         complete_out <= '0';
  56         if e_in.valid = '1' or l_in.valid = '1' then
  57             complete_out <= '1';
  58         end if;
  59
  60         if e_in.exc_write_enable = '1' then
  61             w_out.write_reg <= e_in.exc_write_reg;
  62             w_out.write_data <= e_in.exc_write_data;
  63             w_out.write_enable <= '1';
  64         else
  65             if e_in.write_enable = '1' then
  66                 w_out.write_reg <= e_in.write_reg;
  67                 w_out.write_data <= e_in.write_data;
  68                 w_out.write_enable <= '1';
  69             end if;
  70
  71             if e_in.write_cr_enable = '1' then
  72                 c_out.write_cr_enable <= '1';
  73                 c_out.write_cr_mask <= e_in.write_cr_mask;
  74                 c_out.write_cr_data <= e_in.write_cr_data;
  75             end if;
  76
  77             if e_in.write_xerc_enable = '1' then
  78                 c_out.write_xerc_enable <= '1';
  79                 c_out.write_xerc_data <= e_in.xerc;
  80             end if;
  81
  82             if l_in.write_enable = '1' then
  83                 w_out.write_reg <= l_in.write_reg;
  84                 w_out.write_data <= l_in.write_data;
  85                 w_out.write_enable <= '1';
  86             end if;
  87
  88             if l_in.rc = '1' then
  89                 -- st*cx. instructions
  90                 scf(3) := '0';
  91                 scf(2) := '0';
  92                 scf(1) := l_in.store_done;
  93                 scf(0) := l_in.xerc.so;
  94                 c_out.write_cr_enable <= '1';
  95                 c_out.write_cr_mask <= num_to_fxm(0);
  96                 c_out.write_cr_data(31 downto 28) <= scf;
  97             end if;
  98
  99             -- Perform CR0 update for RC forms
 100             -- Note that loads never have a form with an RC bit, therefore this can test e_in.write_data
 101             if e_in.rc = '1' and e_in.write_enable = '1' then
 102                 zero := not (or e_in.write_data(31 downto 0));
 103                 if e_in.mode_32bit = '0' then
 104                     sign := e_in.write_data(63);
 105                     zero := zero and not (or e_in.write_data(63 downto 32));
 106                 else
 107                     sign := e_in.write_data(31);
 108                 end if;
 109                 c_out.write_cr_enable <= '1';
 110                 c_out.write_cr_mask <= num_to_fxm(0);
 111                 cf(3) := sign;
 112                 cf(2) := not sign and not zero;
 113                 cf(1) := zero;
 114                 cf(0) := e_in.xerc.so;
 115                 c_out.write_cr_data(31 downto 28) <= cf;
 116             end if;
 117         end if;
 118     end process;
 119 end;