writeback.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.crhelpers.all;
   8
   9 entity writeback is
  10     port (
  11         clk          : in std_ulogic;
  12
  13         e_in         : in Execute1ToWritebackType;
  14         l_in         : in Loadstore1ToWritebackType;
  15
  16         w_out        : out WritebackToRegisterFileType;
  17         c_out        : out WritebackToCrFileType;
  18
  19         complete_out : out std_ulogic
  20         );
  21 end entity writeback;
  22
  23 architecture behaviour of writeback is
  24 begin
  25     writeback_1: process(all)
  26         variable x : std_ulogic_vector(0 downto 0);
  27         variable y : std_ulogic_vector(0 downto 0);
  28         variable w : std_ulogic_vector(0 downto 0);
  29         variable cf: std_ulogic_vector(3 downto 0);
  30         variable zero : std_ulogic;
  31         variable sign : std_ulogic;
  32         variable scf  : std_ulogic_vector(3 downto 0);
  33     begin
  34         x(0) := e_in.valid;
  35         y(0) := l_in.valid;
  36         assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
  37
  38         x(0) := e_in.write_enable or e_in.exc_write_enable;
  39         y(0) := l_in.write_enable;
  40         assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
  41
  42         w(0) := e_in.write_cr_enable;
  43         x(0) := (e_in.write_enable and e_in.rc);
  44         assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure;
  45
  46         w_out <= WritebackToRegisterFileInit;
  47         c_out <= WritebackToCrFileInit;
  48
  49         complete_out <= '0';
  50         if e_in.valid = '1' or l_in.valid = '1' then
  51             complete_out <= '1';
  52         end if;
  53
  54         if e_in.exc_write_enable = '1' then
  55             w_out.write_reg <= e_in.exc_write_reg;
  56             w_out.write_data <= e_in.exc_write_data;
  57             w_out.write_enable <= '1';
  58         else
  59             if e_in.write_enable = '1' then
  60                 w_out.write_reg <= e_in.write_reg;
  61                 w_out.write_data <= e_in.write_data;
  62                 w_out.write_enable <= '1';
  63             end if;
  64
  65             if e_in.write_cr_enable = '1' then
  66                 c_out.write_cr_enable <= '1';
  67                 c_out.write_cr_mask <= e_in.write_cr_mask;
  68                 c_out.write_cr_data <= e_in.write_cr_data;
  69             end if;
  70
  71             if e_in.write_xerc_enable = '1' then
  72                 c_out.write_xerc_enable <= '1';
  73                 c_out.write_xerc_data <= e_in.xerc;
  74             end if;
  75
  76             if l_in.write_enable = '1' then
  77                 w_out.write_reg <= gpr_to_gspr(l_in.write_reg);
  78                 w_out.write_data <= l_in.write_data;
  79                 w_out.write_enable <= '1';
  80             end if;
  81
  82             if l_in.rc = '1' then
  83                 -- st*cx. instructions
  84                 scf(3) := '0';
  85                 scf(2) := '0';
  86                 scf(1) := l_in.store_done;
  87                 scf(0) := l_in.xerc.so;
  88                 c_out.write_cr_enable <= '1';
  89                 c_out.write_cr_mask <= num_to_fxm(0);
  90                 c_out.write_cr_data(31 downto 28) <= scf;
  91             end if;
  92
  93             -- Perform CR0 update for RC forms
  94             -- Note that loads never have a form with an RC bit, therefore this can test e_in.write_data
  95             if e_in.rc = '1' and e_in.write_enable = '1' then
  96                 sign := e_in.write_data(63);
  97                 zero := not (or e_in.write_data);
  98                 c_out.write_cr_enable <= '1';
  99                 c_out.write_cr_mask <= num_to_fxm(0);
 100                 cf(3) := sign;
 101                 cf(2) := not sign and not zero;
 102                 cf(1) := zero;
 103                 cf(0) := e_in.xerc.so;
 104                 c_out.write_cr_data(31 downto 28) <= cf;
 105             end if;
 106         end if;
 107     end process;
 108 end;