xilinx-mult.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 library unisim;
   9 use unisim.vcomponents.all;
  10
  11 entity multiply is
  12     port (
  13         clk   : in std_logic;
  14
  15         m_in  : in Execute1ToMultiplyType;
  16         m_out : out MultiplyToExecute1Type
  17         );
  18 end entity multiply;
  19
  20 architecture behaviour of multiply is
  21     signal m00_p, m01_p, m02_p, m03_p : std_ulogic_vector(47 downto 0);
  22     signal m00_pc : std_ulogic_vector(47 downto 0);
  23     signal m10_p, m11_p, m12_p, m13_p : std_ulogic_vector(47 downto 0);
  24     signal m11_pc, m12_pc, m13_pc : std_ulogic_vector(47 downto 0);
  25     signal m20_p, m21_p, m22_p, m23_p : std_ulogic_vector(47 downto 0);
  26     signal s0_pc, s1_pc : std_ulogic_vector(47 downto 0);
  27     signal product_lo : std_ulogic_vector(31 downto 0);
  28     signal product : std_ulogic_vector(127 downto 0);
  29     signal addend : std_ulogic_vector(127 downto 0);
  30     signal s0_carry, p0_carry : std_ulogic_vector(3 downto 0);
  31     signal p0_mask : std_ulogic_vector(47 downto 0);
  32     signal p0_pat, p0_patb : std_ulogic;
  33     signal p1_pat, p1_patb : std_ulogic;
  34
  35     signal req_32bit, r32_1 : std_ulogic;
  36     signal req_neg, rneg_1 : std_ulogic;
  37     signal valid_1 : std_ulogic;
  38
  39 begin
  40     addend <= (others => m_in.neg_result);
  41
  42     m00: DSP48E1
  43         generic map (
  44             ACASCREG => 0,
  45             ALUMODEREG => 0,
  46             AREG => 0,
  47             BCASCREG => 0,
  48             BREG => 0,
  49             CARRYINREG => 0,
  50             CARRYINSELREG => 0,
  51             INMODEREG => 0,
  52             OPMODEREG => 0,
  53             PREG => 0
  54             )
  55         port map (
  56             A => "0000000" & m_in.data1(22 downto 0),
  57             ACIN => (others => '0'),
  58             ALUMODE => "0000",
  59             B => '0' & m_in.data2(16 downto 0),
  60             BCIN => (others => '0'),
  61             C => "00000000000000" & addend(33 downto 0),
  62             CARRYCASCIN => '0',
  63             CARRYIN => '0',
  64             CARRYINSEL => "000",
  65             CEA1 => '0',
  66             CEA2 => '0',
  67             CEAD => '0',
  68             CEALUMODE => '0',
  69             CEB1 => '0',
  70             CEB2 => '0',
  71             CEC => '1',
  72             CECARRYIN => '0',
  73             CECTRL => '0',
  74             CED => '0',
  75             CEINMODE => '0',
  76             CEM => '1',
  77             CEP => '0',
  78             CLK => clk,
  79             D => (others => '0'),
  80             INMODE => "00000",
  81             MULTSIGNIN => '0',
  82             OPMODE => "0110101",
  83             P => m00_p,
  84             PCIN => (others => '0'),
  85             PCOUT => m00_pc,
  86             RSTA => '0',
  87             RSTALLCARRYIN => '0',
  88             RSTALUMODE => '0',
  89             RSTB => '0',
  90             RSTC => '0',
  91             RSTCTRL => '0',
  92             RSTD => '0',
  93             RSTINMODE => '0',
  94             RSTM => '0',
  95             RSTP => '0'
  96             );
  97
  98     m01: DSP48E1
  99         generic map (
 100             ACASCREG => 0,
 101             ALUMODEREG => 0,
 102             AREG => 0,
 103             BCASCREG => 0,
 104             BREG => 0,
 105             CARRYINREG => 0,
 106             CARRYINSELREG => 0,
 107             INMODEREG => 0,
 108             OPMODEREG => 0,
 109             PREG => 0
 110             )
 111         port map (
 112             A => "0000000" & m_in.data1(22 downto 0),
 113             ACIN => (others => '0'),
 114             ALUMODE => "0000",
 115             B => '0' & m_in.data2(33 downto 17),
 116             BCIN => (others => '0'),
 117             C => (others => '0'),
 118             CARRYCASCIN => '0',
 119             CARRYIN => '0',
 120             CARRYINSEL => "000",
 121             CEA1 => '0',
 122             CEA2 => '0',
 123             CEAD => '0',
 124             CEALUMODE => '0',
 125             CEB1 => '0',
 126             CEB2 => '0',
 127             CEC => '1',
 128             CECARRYIN => '0',
 129             CECTRL => '0',
 130             CED => '0',
 131             CEINMODE => '0',
 132             CEM => '1',
 133             CEP => '0',
 134             CLK => clk,
 135             D => (others => '0'),
 136             INMODE => "00000",
 137             MULTSIGNIN => '0',
 138             OPMODE => "1010101",
 139             P => m01_p,
 140             PCIN => m00_pc,
 141             RSTA => '0',
 142             RSTALLCARRYIN => '0',
 143             RSTALUMODE => '0',
 144             RSTB => '0',
 145             RSTC => '0',
 146             RSTCTRL => '0',
 147             RSTD => '0',
 148             RSTINMODE => '0',
 149             RSTM => '0',
 150             RSTP => '0'
 151             );
 152
 153     m02: DSP48E1
 154         generic map (
 155             ACASCREG => 0,
 156             ALUMODEREG => 0,
 157             AREG => 0,
 158             BCASCREG => 0,
 159             BREG => 0,
 160             CARRYINREG => 0,
 161             CARRYINSELREG => 0,
 162             INMODEREG => 0,
 163             OPMODEREG => 0,
 164             PREG => 0
 165             )
 166         port map (
 167             A => "0000000" & m_in.data1(22 downto 0),
 168             ACIN => (others => '0'),
 169             ALUMODE => "0000",
 170             B => '0' & m_in.data2(50 downto 34),
 171             BCIN => (others => '0'),
 172             C => x"0000000" & "000" & addend(50 downto 34),
 173             CARRYCASCIN => '0',
 174             CARRYIN => '0',
 175             CARRYINSEL => "000",
 176             CEA1 => '0',
 177             CEA2 => '0',
 178             CEAD => '0',
 179             CEALUMODE => '0',
 180             CEB1 => '0',
 181             CEB2 => '0',
 182             CEC => '1',
 183             CECARRYIN => '0',
 184             CECTRL => '0',
 185             CED => '0',
 186             CEINMODE => '0',
 187             CEM => '1',
 188             CEP => '0',
 189             CLK => clk,
 190             D => (others => '0'),
 191             INMODE => "00000",
 192             MULTSIGNIN => '0',
 193             OPMODE => "0110101",
 194             P => m02_p,
 195             PCIN => (others => '0'),
 196             RSTA => '0',
 197             RSTALLCARRYIN => '0',
 198             RSTALUMODE => '0',
 199             RSTB => '0',
 200             RSTC => '0',
 201             RSTCTRL => '0',
 202             RSTD => '0',
 203             RSTINMODE => '0',
 204             RSTM => '0',
 205             RSTP => '0'
 206             );
 207
 208     m03: DSP48E1
 209         generic map (
 210             ACASCREG => 0,
 211             ALUMODEREG => 0,
 212             AREG => 0,
 213             BCASCREG => 0,
 214             BREG => 0,
 215             CARRYINREG => 0,
 216             CARRYINSELREG => 0,
 217             INMODEREG => 0,
 218             OPMODEREG => 0,
 219             PREG => 0
 220             )
 221         port map (
 222             A => "0000000" & m_in.data1(22 downto 0),
 223             ACIN => (others => '0'),
 224             ALUMODE => "0000",
 225             B => "00000" & m_in.data2(63 downto 51),
 226             BCIN => (others => '0'),
 227             C => x"000000" & '0' & addend(73 downto 51),
 228             CARRYCASCIN => '0',
 229             CARRYIN => '0',
 230             CARRYINSEL => "000",
 231             CEA1 => '0',
 232             CEA2 => '0',
 233             CEAD => '0',
 234             CEALUMODE => '0',
 235             CEB1 => '0',
 236             CEB2 => '0',
 237             CEC => '1',
 238             CECARRYIN => '0',
 239             CECTRL => '0',
 240             CED => '0',
 241             CEINMODE => '0',
 242             CEM => '1',
 243             CEP => '0',
 244             CLK => clk,
 245             D => (others => '0'),
 246             INMODE => "00000",
 247             MULTSIGNIN => '0',
 248             OPMODE => "0110101",
 249             P => m03_p,
 250             PCIN => (others => '0'),
 251             RSTA => '0',
 252             RSTALLCARRYIN => '0',
 253             RSTALUMODE => '0',
 254             RSTB => '0',
 255             RSTC => '0',
 256             RSTCTRL => '0',
 257             RSTD => '0',
 258             RSTINMODE => '0',
 259             RSTM => '0',
 260             RSTP => '0'
 261             );
 262
 263     m10: DSP48E1
 264         generic map (
 265             ACASCREG => 0,
 266             ALUMODEREG => 0,
 267             AREG => 0,
 268             BCASCREG => 0,
 269             BREG => 0,
 270             CARRYINREG => 0,
 271             CARRYINSELREG => 0,
 272             CREG => 0,
 273             INMODEREG => 0,
 274             OPMODEREG => 0,
 275             PREG => 0
 276             )
 277         port map (
 278             A => "0000000000000" & m_in.data1(39 downto 23),
 279             ACIN => (others => '0'),
 280             ALUMODE => "0000",
 281             B => '0' & m_in.data2(16 downto 0),
 282             BCIN => (others => '0'),
 283             C => x"000" & "00" & m01_p(39 downto 6),
 284             CARRYCASCIN => '0',
 285             CARRYIN => '0',
 286             CARRYINSEL => "000",
 287             CEA1 => '0',
 288             CEA2 => '0',
 289             CEAD => '0',
 290             CEALUMODE => '0',
 291             CEB1 => '0',
 292             CEB2 => '0',
 293             CEC => '0',
 294             CECARRYIN => '0',
 295             CECTRL => '0',
 296             CED => '0',
 297             CEINMODE => '0',
 298             CEM => '1',
 299             CEP => '0',
 300             CLK => clk,
 301             D => (others => '0'),
 302             INMODE => "00000",
 303             MULTSIGNIN => '0',
 304             OPMODE => "0110101",
 305             P => m10_p,
 306             PCIN => (others => '0'),
 307             RSTA => '0',
 308             RSTALLCARRYIN => '0',
 309             RSTALUMODE => '0',
 310             RSTB => '0',
 311             RSTC => '0',
 312             RSTCTRL => '0',
 313             RSTD => '0',
 314             RSTINMODE => '0',
 315             RSTM => '0',
 316             RSTP => '0'
 317             );
 318
 319     m11: DSP48E1
 320         generic map (
 321             ACASCREG => 0,
 322             ALUMODEREG => 0,
 323             AREG => 0,
 324             BCASCREG => 0,
 325             BREG => 0,
 326             CARRYINREG => 0,
 327             CARRYINSELREG => 0,
 328             CREG => 0,
 329             INMODEREG => 0,
 330             OPMODEREG => 0,
 331             PREG => 0
 332             )
 333         port map (
 334             A => "0000000000000" & m_in.data1(39 downto 23),
 335             ACIN => (others => '0'),
 336             ALUMODE => "0000",
 337             B => '0' & m_in.data2(33 downto 17),
 338             BCIN => (others => '0'),
 339             C => x"000" & "00" & m02_p(39 downto 6),
 340             CARRYCASCIN => '0',
 341             CARRYIN => '0',
 342             CARRYINSEL => "000",
 343             CEA1 => '0',
 344             CEA2 => '0',
 345             CEAD => '0',
 346             CEALUMODE => '0',
 347             CEB1 => '0',
 348             CEB2 => '0',
 349             CEC => '0',
 350             CECARRYIN => '0',
 351             CECTRL => '0',
 352             CED => '0',
 353             CEINMODE => '0',
 354             CEM => '1',
 355             CEP => '0',
 356             CLK => clk,
 357             D => (others => '0'),
 358             INMODE => "00000",
 359             MULTSIGNIN => '0',
 360             OPMODE => "0110101",
 361             P => m11_p,
 362             PCIN => (others => '0'),
 363             PCOUT => m11_pc,
 364             RSTA => '0',
 365             RSTALLCARRYIN => '0',
 366             RSTALUMODE => '0',
 367             RSTB => '0',
 368             RSTC => '0',
 369             RSTCTRL => '0',
 370             RSTD => '0',
 371             RSTINMODE => '0',
 372             RSTM => '0',
 373             RSTP => '0'
 374             );
 375
 376     m12: DSP48E1
 377         generic map (
 378             ACASCREG => 0,
 379             ALUMODEREG => 0,
 380             AREG => 0,
 381             BCASCREG => 0,
 382             BREG => 0,
 383             CARRYINREG => 0,
 384             CARRYINSELREG => 0,
 385             CREG => 0,
 386             INMODEREG => 0,
 387             OPMODEREG => 0,
 388             PREG => 0
 389             )
 390         port map (
 391             A => "0000000000000" & m_in.data1(39 downto 23),
 392             ACIN => (others => '0'),
 393             ALUMODE => "0000",
 394             B => '0' & m_in.data2(50 downto 34),
 395             BCIN => (others => '0'),
 396             C => x"0000" & '0' & m03_p(36 downto 6),
 397             CARRYCASCIN => '0',
 398             CARRYIN => '0',
 399             CARRYINSEL => "000",
 400             CEA1 => '0',
 401             CEA2 => '0',
 402             CEAD => '0',
 403             CEALUMODE => '0',
 404             CEB1 => '0',
 405             CEB2 => '0',
 406             CEC => '0',
 407             CECARRYIN => '0',
 408             CECTRL => '0',
 409             CED => '0',
 410             CEINMODE => '0',
 411             CEM => '1',
 412             CEP => '0',
 413             CLK => clk,
 414             D => (others => '0'),
 415             INMODE => "00000",
 416             MULTSIGNIN => '0',
 417             OPMODE => "0110101",
 418             P => m12_p,
 419             PCIN => (others => '0'),
 420             PCOUT => m12_pc,
 421             RSTA => '0',
 422             RSTALLCARRYIN => '0',
 423             RSTALUMODE => '0',
 424             RSTB => '0',
 425             RSTC => '0',
 426             RSTCTRL => '0',
 427             RSTD => '0',
 428             RSTINMODE => '0',
 429             RSTM => '0',
 430             RSTP => '0'
 431             );
 432
 433     m13: DSP48E1
 434         generic map (
 435             ACASCREG => 0,
 436             ALUMODEREG => 0,
 437             AREG => 0,
 438             BCASCREG => 0,
 439             BREG => 0,
 440             CARRYINREG => 0,
 441             CARRYINSELREG => 0,
 442             INMODEREG => 0,
 443             OPMODEREG => 0,
 444             PREG => 0
 445             )
 446         port map (
 447             A => "0000000000000" & m_in.data1(39 downto 23),
 448             ACIN => (others => '0'),
 449             ALUMODE => "0000",
 450             B => "00000" & m_in.data2(63 downto 51),
 451             BCIN => (others => '0'),
 452             C => x"0000000" & "000" & addend(90 downto 74),
 453             CARRYCASCIN => '0',
 454             CARRYIN => '0',
 455             CARRYINSEL => "000",
 456             CEA1 => '0',
 457             CEA2 => '0',
 458             CEAD => '0',
 459             CEALUMODE => '0',
 460             CEB1 => '0',
 461             CEB2 => '0',
 462             CEC => '1',
 463             CECARRYIN => '0',
 464             CECTRL => '0',
 465             CED => '0',
 466             CEINMODE => '0',
 467             CEM => '1',
 468             CEP => '0',
 469             CLK => clk,
 470             D => (others => '0'),
 471             INMODE => "00000",
 472             MULTSIGNIN => '0',
 473             OPMODE => "0110101",
 474             P => m13_p,
 475             PCIN => (others => '0'),
 476             PCOUT => m13_pc,
 477             RSTA => '0',
 478             RSTALLCARRYIN => '0',
 479             RSTALUMODE => '0',
 480             RSTB => '0',
 481             RSTC => '0',
 482             RSTCTRL => '0',
 483             RSTD => '0',
 484             RSTINMODE => '0',
 485             RSTM => '0',
 486             RSTP => '0'
 487             );
 488
 489     m20: DSP48E1
 490         generic map (
 491             ACASCREG => 0,
 492             ALUMODEREG => 0,
 493             AREG => 0,
 494             BCASCREG => 0,
 495             BREG => 0,
 496             CARRYINREG => 0,
 497             CARRYINSELREG => 0,
 498             INMODEREG => 0,
 499             OPMODEREG => 0,
 500             PREG => 0
 501             )
 502         port map (
 503             A => "000000" & m_in.data1(63 downto 40),
 504             ACIN => (others => '0'),
 505             ALUMODE => "0000",
 506             B => '0' & m_in.data2(16 downto 0),
 507             BCIN => (others => '0'),
 508             C => (others => '0'),
 509             CARRYCASCIN => '0',
 510             CARRYIN => '0',
 511             CARRYINSEL => "000",
 512             CEA1 => '0',
 513             CEA2 => '0',
 514             CEAD => '0',
 515             CEALUMODE => '0',
 516             CEB1 => '0',
 517             CEB2 => '0',
 518             CEC => '1',
 519             CECARRYIN => '0',
 520             CECTRL => '0',
 521             CED => '0',
 522             CEINMODE => '0',
 523             CEM => '1',
 524             CEP => '0',
 525             CLK => clk,
 526             D => (others => '0'),
 527             INMODE => "00000",
 528             MULTSIGNIN => '0',
 529             OPMODE => "0010101",
 530             P => m20_p,
 531             PCIN => m11_pc,
 532             RSTA => '0',
 533             RSTALLCARRYIN => '0',
 534             RSTALUMODE => '0',
 535             RSTB => '0',
 536             RSTC => '0',
 537             RSTCTRL => '0',
 538             RSTD => '0',
 539             RSTINMODE => '0',
 540             RSTM => '0',
 541             RSTP => '0'
 542             );
 543
 544     m21: DSP48E1
 545         generic map (
 546             ACASCREG => 0,
 547             ALUMODEREG => 0,
 548             AREG => 0,
 549             BCASCREG => 0,
 550             BREG => 0,
 551             CARRYINREG => 0,
 552             CARRYINSELREG => 0,
 553             INMODEREG => 0,
 554             OPMODEREG => 0,
 555             PREG => 0
 556             )
 557         port map (
 558             A => "000000" & m_in.data1(63 downto 40),
 559             ACIN => (others => '0'),
 560             ALUMODE => "0000",
 561             B => '0' & m_in.data2(33 downto 17),
 562             BCIN => (others => '0'),
 563             C => (others => '0'),
 564             CARRYCASCIN => '0',
 565             CARRYIN => '0',
 566             CARRYINSEL => "000",
 567             CEA1 => '0',
 568             CEA2 => '0',
 569             CEAD => '0',
 570             CEALUMODE => '0',
 571             CEB1 => '0',
 572             CEB2 => '0',
 573             CEC => '1',
 574             CECARRYIN => '0',
 575             CECTRL => '0',
 576             CED => '0',
 577             CEINMODE => '0',
 578             CEM => '1',
 579             CEP => '0',
 580             CLK => clk,
 581             D => (others => '0'),
 582             INMODE => "00000",
 583             MULTSIGNIN => '0',
 584             OPMODE => "0010101",
 585             P => m21_p,
 586             PCIN => m12_pc,
 587             RSTA => '0',
 588             RSTALLCARRYIN => '0',
 589             RSTALUMODE => '0',
 590             RSTB => '0',
 591             RSTC => '0',
 592             RSTCTRL => '0',
 593             RSTD => '0',
 594             RSTINMODE => '0',
 595             RSTM => '0',
 596             RSTP => '0'
 597             );
 598
 599     m22: DSP48E1
 600         generic map (
 601             ACASCREG => 0,
 602             ALUMODEREG => 0,
 603             AREG => 0,
 604             BCASCREG => 0,
 605             BREG => 0,
 606             CARRYINREG => 0,
 607             CARRYINSELREG => 0,
 608             INMODEREG => 0,
 609             OPMODEREG => 0,
 610             PREG => 0
 611             )
 612         port map (
 613             A => "000000" & m_in.data1(63 downto 40),
 614             ACIN => (others => '0'),
 615             ALUMODE => "0000",
 616             B => '0' & m_in.data2(50 downto 34),
 617             BCIN => (others => '0'),
 618             C => (others => '0'),
 619             CARRYCASCIN => '0',
 620             CARRYIN => '0',
 621             CARRYINSEL => "000",
 622             CEA1 => '0',
 623             CEA2 => '0',
 624             CEAD => '0',
 625             CEALUMODE => '0',
 626             CEB1 => '0',
 627             CEB2 => '0',
 628             CEC => '1',
 629             CECARRYIN => '0',
 630             CECTRL => '0',
 631             CED => '0',
 632             CEINMODE => '0',
 633             CEM => '1',
 634             CEP => '0',
 635             CLK => clk,
 636             D => (others => '0'),
 637             INMODE => "00000",
 638             MULTSIGNIN => '0',
 639             OPMODE => "0010101",
 640             P => m22_p,
 641             PCIN => m13_pc,
 642             RSTA => '0',
 643             RSTALLCARRYIN => '0',
 644             RSTALUMODE => '0',
 645             RSTB => '0',
 646             RSTC => '0',
 647             RSTCTRL => '0',
 648             RSTD => '0',
 649             RSTINMODE => '0',
 650             RSTM => '0',
 651             RSTP => '0'
 652             );
 653
 654     m23: DSP48E1
 655         generic map (
 656             ACASCREG => 0,
 657             ALUMODEREG => 0,
 658             AREG => 0,
 659             BCASCREG => 0,
 660             BREG => 0,
 661             CARRYINREG => 0,
 662             CARRYINSELREG => 0,
 663             INMODEREG => 0,
 664             OPMODEREG => 0,
 665             PREG => 0
 666             )
 667         port map (
 668             A => "000000" & m_in.data1(63 downto 40),
 669             ACIN => (others => '0'),
 670             ALUMODE => "0000",
 671             B => "00000" & m_in.data2(63 downto 51),
 672             BCIN => (others => '0'),
 673             C => x"00" & "000" & addend(127 downto 91),
 674             CARRYCASCIN => '0',
 675             CARRYIN => '0',
 676             CARRYINSEL => "000",
 677             CEA1 => '0',
 678             CEA2 => '0',
 679             CEAD => '0',
 680             CEALUMODE => '0',
 681             CEB1 => '0',
 682             CEB2 => '0',
 683             CEC => '1',
 684             CECARRYIN => '0',
 685             CECTRL => '0',
 686             CED => '0',
 687             CEINMODE => '0',
 688             CEM => '1',
 689             CEP => '0',
 690             CLK => clk,
 691             D => (others => '0'),
 692             INMODE => "00000",
 693             MULTSIGNIN => '0',
 694             OPMODE => "0110101",
 695             P => m23_p,
 696             PCIN => (others => '0'),
 697             RSTA => '0',
 698             RSTALLCARRYIN => '0',
 699             RSTALUMODE => '0',
 700             RSTB => '0',
 701             RSTC => '0',
 702             RSTCTRL => '0',
 703             RSTD => '0',
 704             RSTINMODE => '0',
 705             RSTM => '0',
 706             RSTP => '0'
 707             );
 708
 709     s0: DSP48E1
 710         generic map (
 711             ACASCREG => 1,
 712             ALUMODEREG => 0,
 713             AREG => 1,
 714             BCASCREG => 1,
 715             BREG => 1,
 716             CARRYINREG => 0,
 717             CARRYINSELREG => 0,
 718             CREG => 1,
 719             INMODEREG => 0,
 720             MREG => 0,
 721             OPMODEREG => 0,
 722             PREG => 0,
 723             USE_MULT => "none"
 724             )
 725         port map (
 726             A => m22_p(5 downto 0) & x"0000" & m10_p(34 downto 27),
 727             ACIN => (others => '0'),
 728             ALUMODE => "0000",
 729             B => m10_p(26 downto 9),
 730             BCIN => (others => '0'),
 731             C => m20_p(39 downto 0) & m02_p(5 downto 0) & "00",
 732             CARRYCASCIN => '0',
 733             CARRYIN => '0',
 734             CARRYINSEL => "000",
 735             CARRYOUT => s0_carry,
 736             CEA1 => '0',
 737             CEA2 => '1',
 738             CEAD => '0',
 739             CEALUMODE => '0',
 740             CEB1 => '0',
 741             CEB2 => '1',
 742             CEC => '1',
 743             CECARRYIN => '0',
 744             CECTRL => '0',
 745             CED => '0',
 746             CEINMODE => '0',
 747             CEM => '0',
 748             CEP => '0',
 749             CLK => clk,
 750             D => (others => '0'),
 751             INMODE => "00000",
 752             MULTSIGNIN => '0',
 753             OPMODE => "0001111",
 754             PCIN => (others => '0'),
 755             PCOUT => s0_pc,
 756             RSTA => '0',
 757             RSTALLCARRYIN => '0',
 758             RSTALUMODE => '0',
 759             RSTB => '0',
 760             RSTC => '0',
 761             RSTCTRL => '0',
 762             RSTD => '0',
 763             RSTINMODE => '0',
 764             RSTM => '0',
 765             RSTP => '0'
 766             );
 767
 768     s1: DSP48E1
 769         generic map (
 770             ACASCREG => 1,
 771             ALUMODEREG => 0,
 772             AREG => 1,
 773             BCASCREG => 1,
 774             BREG => 1,
 775             CARRYINREG => 0,
 776             CARRYINSELREG => 0,
 777             CREG => 1,
 778             INMODEREG => 0,
 779             MREG => 0,
 780             OPMODEREG => 0,
 781             PREG => 0,
 782             USE_MULT => "none"
 783             )
 784         port map (
 785             A => x"000" & m22_p(41 downto 24),
 786             ACIN => (others => '0'),
 787             ALUMODE => "0000",
 788             B => m22_p(23 downto 6),
 789             BCIN => (others => '0'),
 790             C => m23_p(36 downto 0) & x"00" & "0" & m20_p(41 downto 40),
 791             CARRYCASCIN => '0',
 792             CARRYIN => s0_carry(3),
 793             CARRYINSEL => "000",
 794             CEA1 => '0',
 795             CEA2 => '1',
 796             CEAD => '0',
 797             CEALUMODE => '0',
 798             CEB1 => '0',
 799             CEB2 => '1',
 800             CEC => '1',
 801             CECARRYIN => '0',
 802             CECTRL => '0',
 803             CED => '0',
 804             CEINMODE => '0',
 805             CEM => '0',
 806             CEP => '0',
 807             CLK => clk,
 808             D => (others => '0'),
 809             INMODE => "00000",
 810             MULTSIGNIN => '0',
 811             OPMODE => "0001111",
 812             PCIN => (others => '0'),
 813             PCOUT => s1_pc,
 814             RSTA => '0',
 815             RSTALLCARRYIN => '0',
 816             RSTALUMODE => '0',
 817             RSTB => '0',
 818             RSTC => '0',
 819             RSTCTRL => '0',
 820             RSTD => '0',
 821             RSTINMODE => '0',
 822             RSTM => '0',
 823             RSTP => '0'
 824             );
 825
 826     -- mask is 0 for 32-bit ops, 0x0000ffffffff for 64-bit
 827     p0_mask(47 downto 31) <= (others => '0');
 828     p0_mask(30 downto 0) <= (others => not r32_1);
 829
 830     p0: DSP48E1
 831         generic map (
 832             ACASCREG => 1,
 833             ALUMODEREG => 1,
 834             AREG => 1,
 835             BCASCREG => 1,
 836             BREG => 1,
 837             CARRYINREG => 0,
 838             CARRYINSELREG => 0,
 839             CREG => 1,
 840             INMODEREG => 0,
 841             MREG => 0,
 842             OPMODEREG => 0,
 843             PREG => 0,
 844             SEL_MASK => "C",
 845             USE_MULT => "none",
 846             USE_PATTERN_DETECT => "PATDET"
 847             )
 848         port map (
 849             A => m21_p(22 downto 0) & m03_p(5 downto 0) & '0',
 850             ACIN => (others => '0'),
 851             ALUMODE => "00" & rneg_1 & '0',
 852             B => (others => '0'),
 853             BCIN => (others => '0'),
 854             C => p0_mask,
 855             CARRYCASCIN => '0',
 856             CARRYIN => '0',
 857             CARRYINSEL => "000",
 858             CARRYOUT => p0_carry,
 859             CEA1 => '0',
 860             CEA2 => '1',
 861             CEAD => '0',
 862             CEALUMODE => '1',
 863             CEB1 => '0',
 864             CEB2 => '1',
 865             CEC => '1',
 866             CECARRYIN => '0',
 867             CECTRL => '0',
 868             CED => '0',
 869             CEINMODE => '0',
 870             CEM => '0',
 871             CEP => '0',
 872             CLK => clk,
 873             D => (others => '0'),
 874             INMODE => "00000",
 875             MULTSIGNIN => '0',
 876             OPMODE => "0010011",
 877             P => product(79 downto 32),
 878             PATTERNDETECT => p0_pat,
 879             PATTERNBDETECT => p0_patb,
 880             PCIN => s0_pc,
 881             RSTA => '0',
 882             RSTALLCARRYIN => '0',
 883             RSTALUMODE => '0',
 884             RSTB => '0',
 885             RSTC => '0',
 886             RSTCTRL => '0',
 887             RSTD => '0',
 888             RSTINMODE => '0',
 889             RSTM => '0',
 890             RSTP => '0'
 891             );
 892
 893     p1: DSP48E1
 894         generic map (
 895             ACASCREG => 1,
 896             ALUMODEREG => 1,
 897             AREG => 1,
 898             BCASCREG => 1,
 899             BREG => 1,
 900             CARRYINREG => 0,
 901             CARRYINSELREG => 0,
 902             CREG => 0,
 903             INMODEREG => 0,
 904             MASK => x"000000000000",
 905             MREG => 0,
 906             OPMODEREG => 0,
 907             PREG => 0,
 908             USE_MULT => "none",
 909             USE_PATTERN_DETECT => "PATDET"
 910             )
 911         port map (
 912             A => x"0000000" & '0' & m21_p(41),
 913             ACIN => (others => '0'),
 914             ALUMODE => "00" & rneg_1 & '0',
 915             B => m21_p(40 downto 23),
 916             BCIN => (others => '0'),
 917             C => (others => '0'),
 918             CARRYCASCIN => '0',
 919             CARRYIN => p0_carry(3),
 920             CARRYINSEL => "000",
 921             CEA1 => '0',
 922             CEA2 => '1',
 923             CEAD => '0',
 924             CEALUMODE => '1',
 925             CEB1 => '0',
 926             CEB2 => '1',
 927             CEC => '0',
 928             CECARRYIN => '0',
 929             CECTRL => '0',
 930             CED => '0',
 931             CEINMODE => '0',
 932             CEM => '0',
 933             CEP => '0',
 934             CLK => clk,
 935             D => (others => '0'),
 936             INMODE => "00000",
 937             MULTSIGNIN => '0',
 938             OPMODE => "0010011",
 939             P => product(127 downto 80),
 940             PATTERNDETECT => p1_pat,
 941             PATTERNBDETECT => p1_patb,
 942             PCIN => s1_pc,
 943             RSTA => '0',
 944             RSTALLCARRYIN => '0',
 945             RSTALUMODE => '0',
 946             RSTB => '0',
 947             RSTC => '0',
 948             RSTCTRL => '0',
 949             RSTD => '0',
 950             RSTINMODE => '0',
 951             RSTM => '0',
 952             RSTP => '0'
 953             );
 954
 955     product(31 downto 0) <= product_lo xor (31 downto 0 => req_neg);
 956
 957     mult_out: process(all)
 958         variable ov : std_ulogic;
 959     begin
 960         -- set overflow if the high bits are neither all zeroes nor all ones
 961         if req_32bit = '0' then
 962             ov := not ((p1_pat and p0_pat) or (p1_patb and p0_patb));
 963         else
 964             ov := not ((p1_pat and p0_pat and not product(31)) or
 965                        (p1_patb and p0_patb and product(31)));
 966         end if;
 967
 968         m_out.result <= product;
 969         m_out.overflow <= ov;
 970     end process;
 971
 972     process(clk)
 973     begin
 974         if rising_edge(clk) then
 975             product_lo <= m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0);
 976             m_out.valid <= valid_1;
 977             valid_1 <= m_in.valid;
 978             req_32bit <= r32_1;
 979             r32_1 <= m_in.is_32bit;
 980             req_neg <= rneg_1;
 981             rneg_1 <= m_in.neg_result;
 982         end if;
 983     end process;
 984
 985 end architecture behaviour;