# Pinouts (PinMux) auto-generated by [[pinouts.py]] [[!toc ]] ## Bank N (32 pins, width 2) | Pin | Mux0 | Mux1 | Mux2 | Mux3 | | --- | ----------- | ----------- | ----------- | ----------- | | 6 | N VSSE_6 | | | 7 | N VDDE_6 | | | 8 | N VDDI_6 | | | 9 | N VSSI_6 | | | 22 | N VSSI_7 | | | 23 | N VDDI_7 | | | 24 | N VSSE_7 | | | 25 | N VDDE_7 | | | 27 | N SYS_RST | | | 28 | N SYS_PLLCLK | | | 29 | N SYS_PLLSELA0 | | | 30 | N SYS_PLLSELA1 | | | 31 | N SYS_PLLTESTOUT | | ## Bank E (32 pins, width 2) | Pin | Mux0 | Mux1 | Mux2 | Mux3 | | --- | ----------- | ----------- | ----------- | ----------- | | 32 | E GPIOE_E0 | | | 33 | E GPIOE_E1 | | | 34 | E GPIOE_E2 | | | 35 | E GPIOE_E3 | | | 36 | E GPIOE_E4 | | | 37 | E GPIOE_E5 | | | 38 | E VSSE_4 | | | 39 | E VDDE_4 | | | 40 | E VDDI_4 | | | 41 | E VSSI_4 | | | 42 | E GPIOE_E6 | | | 43 | E GPIOE_E7 | | | 44 | E GPIOE_E8 | | | 45 | E JTAG_TMS | | | 46 | E JTAG_TDI | | | 47 | E JTAG_TDO | | | 48 | E JTAG_TCK | | | 49 | E GPIOE_E9 | | | 50 | E GPIOE_E10 | | | 51 | E GPIOE_E11 | | | 52 | E GPIOE_E12 | | | 53 | E GPIOE_E13 | | | 54 | E VSSI_5 | | | 55 | E VDDI_5 | | | 56 | E VSSE_5 | | | 57 | E VDDE_5 | | | 58 | E GPIOE_E14 | | | 59 | E GPIOE_E15 | | | 60 | E EINT_0 | | | 61 | E EINT_1 | | | 62 | E EINT_2 | | | 63 | E SYS_PLLVCOUT | | ## Bank S (32 pins, width 2) | Pin | Mux0 | Mux1 | Mux2 | Mux3 | | --- | ----------- | ----------- | ----------- | ----------- | | 64 | S SDR_AD10 | | | 65 | S SDR_AD11 | | | 66 | S SDR_AD12 | | | 67 | S SDR_DQM1 | | | 68 | S VDDE_2 | | | 69 | S VSSE_2 | | | 70 | S VDDI_2 | | | 71 | S VSSI_2 | | | 72 | S SDR_D8 | | | 73 | S SDR_D9 | | | 74 | S SDR_D10 | | | 75 | S SDR_D11 | | | 76 | S SDR_D12 | | | 77 | S SDR_D13 | | | 78 | S SDR_D14 | | | 79 | S SDR_D15 | | | 80 | S SDR_CLK | | | 81 | S SDR_CKE | | | 82 | S SDR_RASn | | | 83 | S SDR_CASn | | | 84 | S SDR_WEn | | | 85 | S SDR_CSn0 | | | 86 | S VSSI_3 | | | 87 | S VDDI_3 | | | 88 | S VSSE_3 | | | 89 | S VDDE_3 | | | 90 | S UART0_TX | | | 91 | S UART0_RX | | | 92 | S MSPI0_CK | | | 93 | S MSPI0_NSS | | | 94 | S MSPI0_MOSI | | | 95 | S MSPI0_MISO | | ## Bank W (32 pins, width 2) | Pin | Mux0 | Mux1 | Mux2 | Mux3 | | --- | ----------- | ----------- | ----------- | ----------- | | 96 | W SDR_AD9 | | | 97 | W SDR_AD8 | | | 98 | W SDR_AD7 | | | 99 | W SDR_AD6 | | | 100 | W SDR_AD5 | | | 101 | W SDR_AD4 | | | 102 | W VDDE_0 | | | 103 | W VSSE_0 | | | 104 | W VDDI_0 | | | 105 | W VSSI_0 | | | 106 | W SDR_AD3 | | | 107 | W SDR_AD2 | | | 108 | W SDR_AD1 | | | 109 | W SDR_AD0 | | | 110 | W SDR_BA1 | | | 111 | W SDR_BA0 | | | 112 | W SDR_D7 | | | 113 | W SDR_D6 | | | 114 | W SDR_D5 | | | 115 | W SDR_D4 | | | 116 | W SDR_D3 | | | 117 | W SDR_D2 | | | 118 | W SDR_D1 | | | 119 | W SDR_D0 | | | 120 | W SDR_DQM0 | | | 122 | W MTWI_SDA | | | 123 | W MTWI_SCL | | | 124 | W VSSI_1 | | | 125 | W VDDI_1 | | | 126 | W VSSE_1 | | | 127 | W VDDE_1 | | # Pinouts (Fixed function) # Functions (PinMux) auto-generated by [[pinouts.py]] ## EINT External Interrupt * EINT_0 : E28/0 * EINT_1 : E29/0 * EINT_2 : E30/0 ## GPIO GPIO * GPIOE_E0 : E0/0 * GPIOE_E1 : E1/0 * GPIOE_E10 : E18/0 * GPIOE_E11 : E19/0 * GPIOE_E12 : E20/0 * GPIOE_E13 : E21/0 * GPIOE_E14 : E26/0 * GPIOE_E15 : E27/0 * GPIOE_E2 : E2/0 * GPIOE_E3 : E3/0 * GPIOE_E4 : E4/0 * GPIOE_E5 : E5/0 * GPIOE_E6 : E10/0 * GPIOE_E7 : E11/0 * GPIOE_E8 : E12/0 * GPIOE_E9 : E17/0 ## JTAG JTAG * JTAG_TCK : E16/0 * JTAG_TDI : E14/0 * JTAG_TDO : E15/0 * JTAG_TMS : E13/0 ## MSPI0 SPI Master 1 (general) * MSPI0_CK : S28/0 * MSPI0_MISO : S31/0 * MSPI0_MOSI : S30/0 * MSPI0_NSS : S29/0 ## MTWI I2C Master 1 * MTWI_SCL : W27/0 * MTWI_SDA : W26/0 ## SDR SDRAM * SDR_AD0 : W13/0 * SDR_AD1 : W12/0 * SDR_AD10 : S0/0 * SDR_AD11 : S1/0 * SDR_AD12 : S2/0 * SDR_AD2 : W11/0 * SDR_AD3 : W10/0 * SDR_AD4 : W5/0 * SDR_AD5 : W4/0 * SDR_AD6 : W3/0 * SDR_AD7 : W2/0 * SDR_AD8 : W1/0 * SDR_AD9 : W0/0 * SDR_BA0 : W15/0 * SDR_BA1 : W14/0 * SDR_CASn : S19/0 * SDR_CKE : S17/0 * SDR_CLK : S16/0 * SDR_CSn0 : S21/0 * SDR_D0 : W23/0 * SDR_D1 : W22/0 * SDR_D10 : S10/0 * SDR_D11 : S11/0 * SDR_D12 : S12/0 * SDR_D13 : S13/0 * SDR_D14 : S14/0 * SDR_D15 : S15/0 * SDR_D2 : W21/0 * SDR_D3 : W20/0 * SDR_D4 : W19/0 * SDR_D5 : W18/0 * SDR_D6 : W17/0 * SDR_D7 : W16/0 * SDR_D8 : S8/0 * SDR_D9 : S9/0 * SDR_DQM0 : W24/0 * SDR_DQM1 : S3/0 * SDR_RASn : S18/0 * SDR_WEn : S20/0 ## SYS System Control * SYS_PLLCLK : N28/0 * SYS_PLLSELA0 : N29/0 * SYS_PLLSELA1 : N30/0 * SYS_PLLTESTOUT : N31/0 * SYS_PLLVCOUT : E31/0 * SYS_RST : N27/0 ## UART0 UART (TX/RX) 1 * UART0_RX : S27/0 * UART0_TX : S26/0 ## VDD Power * VDDE_0 : W6/0 * VDDE_1 : W31/0 * VDDE_2 : S4/0 * VDDE_3 : S25/0 * VDDE_4 : E7/0 * VDDE_5 : E25/0 * VDDE_6 : N7/0 * VDDE_7 : N25/0 * VDDI_0 : W8/0 * VDDI_1 : W29/0 * VDDI_2 : S6/0 * VDDI_3 : S23/0 * VDDI_4 : E8/0 * VDDI_5 : E23/0 * VDDI_6 : N8/0 * VDDI_7 : N23/0 ## VSS GND * VSSE_0 : W7/0 * VSSE_1 : W30/0 * VSSE_2 : S5/0 * VSSE_3 : S24/0 * VSSE_4 : E6/0 * VSSE_5 : E24/0 * VSSE_6 : N6/0 * VSSE_7 : N24/0 * VSSI_0 : W9/0 * VSSI_1 : W28/0 * VSSI_2 : S7/0 * VSSI_3 : S22/0 * VSSI_4 : E9/0 * VSSI_5 : E22/0 * VSSI_6 : N9/0 * VSSI_7 : N22/0 # Pinmap for Libre-SOC 180nm ## UART0 * UART0_TX 90 S26/0 * UART0_RX 91 S27/0 ## GPIOS ## GPIOE * GPIOE_E0 32 E0/0 * GPIOE_E1 33 E1/0 * GPIOE_E2 34 E2/0 * GPIOE_E3 35 E3/0 * GPIOE_E4 36 E4/0 * GPIOE_E5 37 E5/0 * GPIOE_E6 42 E10/0 * GPIOE_E7 43 E11/0 * GPIOE_E8 44 E12/0 * GPIOE_E9 49 E17/0 * GPIOE_E10 50 E18/0 * GPIOE_E11 51 E19/0 * GPIOE_E12 52 E20/0 * GPIOE_E13 53 E21/0 * GPIOE_E14 58 E26/0 * GPIOE_E15 59 E27/0 ## JTAG * JTAG_TMS 45 E13/0 * JTAG_TDI 46 E14/0 * JTAG_TDO 47 E15/0 * JTAG_TCK 48 E16/0 ## PWM ## EINT * EINT_0 60 E28/0 * EINT_1 61 E29/0 * EINT_2 62 E30/0 ## VDD * VDDE_6 7 N7/0 * VDDI_6 8 N8/0 * VDDI_7 23 N23/0 * VDDE_7 25 N25/0 * VDDE_4 39 E7/0 * VDDI_4 40 E8/0 * VDDI_5 55 E23/0 * VDDE_5 57 E25/0 ## VSS * VSSE_6 6 N6/0 * VSSI_6 9 N9/0 * VSSI_7 22 N22/0 * VSSE_7 24 N24/0 * VSSE_4 38 E6/0 * VSSI_4 41 E9/0 * VSSI_5 54 E22/0 * VSSE_5 56 E24/0 ## SYS * SYS_RST 27 N27/0 * SYS_PLLCLK 28 N28/0 * SYS_PLLSELA0 29 N29/0 * SYS_PLLSELA1 30 N30/0 * SYS_PLLTESTOUT 31 N31/0 * SYS_PLLVCOUT 63 E31/0 ## MTWI I2C. * MTWI_SDA 122 W26/0 * MTWI_SCL 123 W27/0 ## MSPI0 * MSPI0_CK 92 S28/0 * MSPI0_NSS 93 S29/0 * MSPI0_MOSI 94 S30/0 * MSPI0_MISO 95 S31/0 ## SDR * SDR_AD10 64 S0/0 * SDR_AD11 65 S1/0 * SDR_AD12 66 S2/0 * SDR_DQM1 67 S3/0 * SDR_D8 72 S8/0 * SDR_D9 73 S9/0 * SDR_D10 74 S10/0 * SDR_D11 75 S11/0 * SDR_D12 76 S12/0 * SDR_D13 77 S13/0 * SDR_D14 78 S14/0 * SDR_D15 79 S15/0 * SDR_CLK 80 S16/0 * SDR_CKE 81 S17/0 * SDR_RASn 82 S18/0 * SDR_CASn 83 S19/0 * SDR_WEn 84 S20/0 * SDR_CSn0 85 S21/0 * SDR_AD9 96 W0/0 * SDR_AD8 97 W1/0 * SDR_AD7 98 W2/0 * SDR_AD6 99 W3/0 * SDR_AD5 100 W4/0 * SDR_AD4 101 W5/0 * SDR_AD3 106 W10/0 * SDR_AD2 107 W11/0 * SDR_AD1 108 W12/0 * SDR_AD0 109 W13/0 * SDR_BA1 110 W14/0 * SDR_BA0 111 W15/0 * SDR_D7 112 W16/0 * SDR_D6 113 W17/0 * SDR_D5 114 W18/0 * SDR_D4 115 W19/0 * SDR_D3 116 W20/0 * SDR_D2 117 W21/0 * SDR_D1 118 W22/0 * SDR_D0 119 W23/0 * SDR_DQM0 120 W24/0 ## Unused Pinouts (spare as GPIO) for 'Libre-SOC 180nm' | Pin | Mux0 | Mux1 | Mux2 | Mux3 | | --- | ----------- | ----------- | ----------- | ----------- | | 68 | S VDDE_2 | | | | | 69 | S VSSE_2 | | | | | 70 | S VDDI_2 | | | | | 71 | S VSSI_2 | | | | | 86 | S VSSI_3 | | | | | 87 | S VDDI_3 | | | | | 88 | S VSSE_3 | | | | | 89 | S VDDE_3 | | | | | 102 | W VDDE_0 | | | | | 103 | W VSSE_0 | | | | | 104 | W VDDI_0 | | | | | 105 | W VSSI_0 | | | | | 124 | W VSSI_1 | | | | | 125 | W VDDI_1 | | | | | 126 | W VSSE_1 | | | | | 127 | W VDDE_1 | | | | # Reference Datasheets datasheets and pinout links * * * * p8 * * * * ULPI OTG PHY, ST * ULPI OTG PHY, TI TUSB1210 # Pin Bank starting points and lengths * E 32 32 2 * N 0 32 2 * S 64 32 2 * W 96 32 2