# Welcome to Libre-SoC(formerly Libre-RISCV)!

The Libre-SoC project is an effort to develop an completely 
SOC that is libre to the bedrock.

Libre has a very specific meaning and guarantees, where "open" does not.
See <https://www.gnu.org/philosophy/open-source-misses-the-point.html>
for an explanation of the distinction, and for additional examples:
<https://wiki.opensourceecology.org/wiki/Fake_Open_Source>

This is a publicly editable wiki.

All wikis are supposed to have a [[SandBox]], so this one does too.

This wiki is powered by [[ikiwiki]].

This is the sitemap: [[sitemap]]

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# Contact

The main contact point is the 
[mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev).
If you need to contact the sysadmin please use webmaster@libre-ruecv.org

# Joining/Onboarding Process

This process probably needs some improvement: the basic 
idea is to join the
[mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
introduce yourself, and read through
[recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
and the [[charter]].

The next thing you should do is read through the [bugs
list](http://bugs.libre-riscv.org) and see if there are any bugs that
pique your interest.

We do have funding available (see [[nlnet]]) upon completion of issues -
we are also working on procuring more funding which gets the project to
nanometre scale tapeout.

After all this, if you feel that Libre-SOC is a good cause that
you would like to contribute to, add yourself to the [[current_members]]
page and fill in some information about yourself.

## Needed Skills

Most labor is currently being applied to developing the GPU portion of
the LibreSOC.

The highest priority needed at the moment is a c++ engineer to work on
a MESA 3D driver. This will begin life as similar to SwiftShader however
retaining the vectorisation and predication intrinsics.

Medium to long-term we need HDL engineers. Particularly those familiar
with nMigen or just python.  Most of the techniques being used require
software engineering skills (OO design, polymorphism) than they do more
traditional HDL programming skills. Basically if you have experience in 2
of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
design. See [[HDL_workflow]]

Also, individuals with experience in formal mathematical verification
are quite welcome.

TODO: add a list of upcoming project tasks/milestones (link to
bugtracker).

# Resources

* Mailing Lists <http://lists.libre-riscv.org> -
  Archives at <http://lists.libre-riscv.org/pipermail>
* Git repositories <http://git.libre-riscv.org>
  may be cloned publicly with
  git clone https://git.libre-riscv.org/git/repositoryname.git
* Bugzilla at <http://bugs.libre-riscv.org/>
* Kazan (Vulkan driver) at <https://salsa.debian.org/Kazan-team/kazan>
* Further Information [[resources]]

# Main Pages

* Libre-SoC [[charter]]
* [[shakti/m_class]]
* [[alt_rvp]]
* [[3d_gpu]]
* [[vpu]]
* [[simple_v_extension]]
* [[zfpacc_proposal]]
* [[ztrans_proposal]]
* [[simple_v_extension/specification/mv.x]]
* [[simple_v_extension/specification/ld.x]]
* Specifications and [[resources]]

# Spike Emulator
* [Set-Up Instructions][1]

[1]: https://libre-riscv.org/3d_gpu/spike_sv/

# Current Members

[[current_members]]