#include "riscv_test.h"
#include "sv_test_macros.h"

RVTEST_RV64U        # Define TVM used by program.


# SV test: vector-vector add different rd and rs1
#
# sets up x6 and x7 with data, sets VL to 2, and carries out
# an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"

# Test code region.
RVTEST_CODE_BEGIN   # Start of test code.

        .option norvc

        SV_LD_DATA( x6, testdata+0 , 0)
        SV_LD_DATA( x7, testdata+8, 0)
        SV_LD_DATA( x8, testdata+16, 0)

        li          x3, 0 # deliberately set x3 to 0 (target of add)
        li          x4, 0 # deliberately set x4 to 0
        li          x5, 0 # deliberately set x4 to 0

        SET_SV_MVL(3)
        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),
                      SV_REG_CSR(1, 6, 0, 6, 1) )
        SET_SV_VL(3)

        .option rvc
        c.mv    x3, x6
        .option norvc

        SET_SV_VL(0)
        CLR_SV_CSRS()
        SET_SV_MVL(0)

        TEST_SV_IMM(x3, 1001) # should not be modified
        TEST_SV_IMM(x4, 41)
        TEST_SV_IMM(x5, 42)

        RVTEST_PASS           # Signal success.
fail:
        RVTEST_FAIL
RVTEST_CODE_END     # End of test code.

# Input data section.
# This section is optional, and this data is NOT saved in the output.
.data
        .align 3
testdata:
        .dword 1001
        .dword 41
        .dword 42

# Output data section.
RVTEST_DATA_BEGIN   # Start of test output data region.
        .align 3
result:
        .dword -1
        .dword -1
        .dword -1
RVTEST_DATA_END     # End of test output data region.