#include "riscv_test.h"
#include "sv_test_macros.h"

RVTEST_RV64U        # Define TVM used by program.


#define SV_PRED_C_MV_TEST( pred1, pred2, expect1, expect2, expect3 ) \
                                                       \
        SV_LD_DATA( x6, testdata+0 , 0);               \
        SV_LD_DATA( x7, testdata+8, 0);                \
        SV_LD_DATA( x8, testdata+16, 0);               \
                                                       \
        li          x3, 2;                             \
        li          x4, 3;                             \
        li          x5, 4;                             \
        li          a3, pred1;                         \
        li          a4, pred2;                         \
                                                       \
        SET_SV_MVL(3);                                 \
        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),       \
                      SV_REG_CSR(1, 6, 0, 6, 1) );     \
        SET_SV_2PREDCSRS(                              \
                      SV_PRED_CSR(1, 3, 0, 0, 13, 0),  \
                      SV_PRED_CSR(1, 6, 0, 0, 14, 0) );\
        SET_SV_VL(3);                                  \
                                                       \
        .option rvc;                                   \
        c.mv    x3, x6;                                \
        .option norvc;                                 \
                                                       \
        SET_SV_VL(0);                                  \
        CLR_SV_CSRS();                                 \
        SET_SV_MVL(0);                                 \
                                                       \
        TEST_SV_IMM(x3, expect1);                      \
        TEST_SV_IMM(x4, expect2);                      \
        TEST_SV_IMM(x5, expect3);

# SV test: vector-vector add different rd and rs1
#
# sets up x6 and x7 with data, sets VL to 2, and carries out
# an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"

# Test code region.
RVTEST_CODE_BEGIN   # Start of test code.

        .option norvc

        SV_PRED_C_MV_TEST( 0x7, 0x7, 1001, 41, 42 )
        SV_PRED_C_MV_TEST( 0x3, 0x7, 1001, 41, 4 )
        SV_PRED_C_MV_TEST( 0x1, 0x7, 1001, 3, 4 )

        SV_PRED_C_MV_TEST( 0x6, 0x7, 2, 1001, 41 )
        SV_PRED_C_MV_TEST( 0x6, 0x3, 2, 1001, 41 )
        SV_PRED_C_MV_TEST( 0x6, 0x1, 2, 1001, 4 )
        SV_PRED_C_MV_TEST( 0x6, 0x6, 2, 41, 42 )

        SV_PRED_C_MV_TEST( 0x5, 0x6, 41, 3, 42 )

        SV_PRED_C_MV_TEST( 0x1, 0x1, 1001, 3, 4 )
        SV_PRED_C_MV_TEST( 0x2, 0x1, 2, 1001, 4 )
        SV_PRED_C_MV_TEST( 0x4, 0x1, 2, 3, 1001 )

        SV_PRED_C_MV_TEST( 0x1, 0x1, 1001, 3, 4 )
        SV_PRED_C_MV_TEST( 0x1, 0x2, 41, 3, 4 )
        SV_PRED_C_MV_TEST( 0x1, 0x4, 42, 3, 4 )

        RVTEST_PASS           # Signal success.
fail:
        RVTEST_FAIL
RVTEST_CODE_END     # End of test code.

# Input data section.
# This section is optional, and this data is NOT saved in the output.
.data
        .align 3
testdata:
        .dword 1001
        .dword 41
        .dword 42

# Output data section.
RVTEST_DATA_BEGIN   # Start of test output data region.
        .align 3
result:
        .dword -1
        .dword -1
        .dword -1
RVTEST_DATA_END     # End of test output data region.