#include "riscv_test.h"
#include "sv_test_macros.h"

RVTEST_RV64UF


# SV test: vector-vector fadd
#
# sets up x3 and x4 with data, sets VL to 2, and carries out
# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"

# Test code region.
RVTEST_CODE_BEGIN   # Start of test code.

        SV_FLW_DATA( f4, testdata+0 , 0)
        SV_FLW_DATA( f5, testdata+4, 0)
        SV_FLW_DATA( f6, testdata+8, 0)
        SV_FLW_DATA( f7, testdata+12, 0)

        SET_SV_MVL(2)
        SET_SV_3CSRS( SV_REG_CSR(0, 2, 0, 2, 1),
                      SV_REG_CSR(0, 4, 0, 4, 1),
                      SV_REG_CSR(0, 6, 0, 6, 1) )
        SET_SV_VL(2)

        fadd.s f2, f4, f6;

        CLR_SV_CSRS()
        SET_SV_VL(1)
        SET_SV_MVL(1)

        TEST_SV_FW(0, f2, answer+0, 0) 
        TEST_SV_FW(0, f3, answer+4, 0) 

        RVTEST_PASS           # Signal success.
fail:
        RVTEST_FAIL
RVTEST_CODE_END     # End of test code.

# Input data section.
# This section is optional, and this data is NOT saved in the output.
.data
        .align 3
testdata:
        .float 41.0
        .float 42.0
        .float 1.0
        .float 2.0
answer:
        #.word 0x5140
        #.word 0x5100
        .float 42.0
        .float 44.0

# Output data section.
RVTEST_DATA_BEGIN   # Start of test output data region.
        .align 3
result:
        .dword -1
        .dword -1
        .dword -1
RVTEST_DATA_END     # End of test output data region.