#include "riscv_test.h" #include "sv_test_macros.h" RVTEST_RV64U # Define TVM used by program. # SV test: vector-vector add # # sets up x3 and x4 with data, sets VL to 2, and carries out # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4" # Test code region. RVTEST_CODE_BEGIN # Start of test code. SV_ELWIDTH_TEST_LOAD(ld, la, testdata, 8, 2, SV_W_DFLT, SV_W_DFLT, SV_W_DFLT, 0, 0, 1, 0x8979695949392919, 0x8777675747372717, 0xa5a5a5a5a5a5a5a5) SV_ELWIDTH_TEST_LOAD(ld, la, testdata, 8, 3, SV_W_DFLT, SV_W_DFLT, SV_W_DFLT, 0, 0, 1, 0x8979695949392919, 0x8777675747372717, 0x8676665646362616) SV_ELWIDTH_TEST_LOAD(ld, la, testdata, 8, 3, SV_W_16BIT, SV_W_16BIT, SV_W_DFLT, 0, 0, 1, 0x0000000000002919, 0x0000000000004939, 0x0000000000006959) SV_ELWIDTH_TEST_LOAD(ld, la, testdata, 8, 5, SV_W_16BIT, SV_W_16BIT, SV_W_32BIT, 0, 0, 1, 0x0000493900002919, 0xffff897900006959, 0xa5a5a5a500002717) SV_ELWIDTH_TEST_LOAD(ld, la, testdata, 8, 5, SV_W_32BIT, SV_W_32BIT, SV_W_16BIT, 0, 0, 1, 0x6757271769592919, 0xa5a5a5a5a5a52616, 0xa5a5a5a5a5a5a5a5) SV_ELWIDTH_TEST_LOAD(ld, la, testdata, 8, 7, SV_W_16BIT, SV_W_16BIT, SV_W_8BIT, 0, 0, 1, 0xa557371779593919, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5) SV_ELWIDTH_TEST_LOAD(ld, la, testdata, 8, 11, SV_W_8BIT, SV_W_8BIT, SV_W_16BIT, 0, 0, 1, 0x0049003900290019, 0xff89007900690059, 0xa5a5003700270017) RVTEST_PASS # Signal success. fail: RVTEST_FAIL RVTEST_CODE_END # End of test code. # Input data section. # This section is optional, and this data is NOT saved in the output. .data .align 3 testdata: .dword 0x8979695949392919 .dword 0x8777675747372717 .dword 0x8676665646362616 .dword 0x8272625242322212 .dword 0x8171615141312111 .dword 0x8373635343332313 # Output data section. RVTEST_DATA_BEGIN # Start of test output data region. .align 3 result: .dword -1 .dword -1 .dword -1 RVTEST_DATA_END # End of test output data region.