# Friday 24th November 17:00 UTC

- A meeting with Dmitry, David, James, Luke, and Andrey to explain the
new grants for updating Simple-V for RISC-V (first implemented 4 years
ago, now in need of an update)

Main points to take away:

- There will be two new grants (links below).
- Meeting on Tuesday will be used for planning the binutils grant.
Link to next week's meeting: [[meetings/sync_up/sync_up_2023-11-28]]

## New SV Expansion Grant

- [[nlnet_2023_simplev_riscv]]

The expansion grant. Primary focus on:

- Add RISC-V ISA support to ISACAller.
- Extend `svanalysis.py` for characterising RISC-V instructions
(number of reg ports, insn type, etc.). Link to existing
[svanalysis.py](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;h=21778ad02d78c4f7ef5b6df93e096f4abbe365ad;hb=HEAD)
- Extending existing sv for of the RISC-V Spike sim to support
full feature set of SimpleV. Link to LibreSOC'
[sv spike repo](https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv)

## New Binutils Grant

- [[nlnet_2023_simplev_riscv_binutils]]

- Primarily Dmitry doing most of the work.
- Communication on Simple-V formats to be defined by luke and jacob

## Primary Tasks

  1. Finish writing libopid, some of the work started 4 months ago
(no RfPs can be submitted for that work). Link to
[repo](https://git.libre-soc.org/?p=mdis.git;a=summary)
  2. Convert existing PowerISA (SFFS) `isndb` instruction database to libopid
   (without losing CSV files which are machine-readable by other projects)
  3. Create RISC-V instruction database using libopid.
  4. Implement SVP64 PowerISA in libopid.
  5. Implement SimpleV for RISC-V in libopid.
     - SVP32 (16+16) - 16-bit prefix for 16-bit compressed instructions.
     - SVP48 (16+32) - 16-bit prefix for 32-bit instructions.
     - SVP64 (32+32) - 32-bit prefix for 64-bit instructions.

* The 16-bit prefix saves instruction space in memory
 (but with limited feature set: 128 regs span but cruder spacing).
* The 32-bit prefix gives full access to SimpleV feature set
 (128 regs, all SV modes such as data dependent fail-first, etc.)

# Defining SVPxxSingle

Another point mentioned after Dmitry left is the need to define SVPxxSingle.
[[openpower/sv/svp64-single]]

For both RISC-V and PowerISA need to define:

- SVP16Single
- SVP32Single
- SVP64Single

*(Andrey: Why do these need to be defined for PowerISA?
A: see page and bugreport. full 128 reg access)*

Doing this work for both ISAs at the same time isn't too difficult,
as the SVPxxSingle format will be the same for both ISAs.
By defining SV format to be the same across ISAs saves effort
and helps future programmers to switch from one ISA to another
with minimal adjustment...*perhaps except for x86*...)

[[!tag meeting2023]]