# NL.net proposal


## Project name

OpenPOWER ISA RFCs

## Website / wiki 

<https://libre-soc.org/nlnet_2022_opf_isa_wg>

Please be short and to the point in your answers; focus primarily on
the what and how, not so much on the why. Add longer descriptions as
attachments (see below). If English isn't your first language, don't
worry - our reviewers don't care about spelling errors, only about
great ideas. We apologise for the inconvenience of having to submit in
English. On the up side, you can be as technical as you need to be (but
you don't have to). Do stay concrete. Use plain text in your reply only,
if you need any HTML to make your point please include this as attachment.

## Abstract: Can you explain the whole project and its expected outcome(s).

The current NLnet funding to date has allowed Libre-SOC to develop
one of the most powerful Scalable Vector ISAs in the world.
The 25-year-old Power ISA, developed and curated by IBM, was
transferred to the OpenPOWER Foundation, and is the basis of
Simple-V, the Draft Scalable Vector Extension.

Simple-V *needs* to be submitted to the OPF ISA Working Group,
for formal discussion and inclusion. Given that it is 380
pages we expect this to be done carefully and incrementally.
https://ftp.libre-soc.org/simple_v_spec.pdf

However the
process of submitting Requests For Change, at the time of writing,
still has not been publicly announced and opened up. We expect it
to be very soon, but obviously could not begin any RFC Submission as
part of the earlier NLnet funding.

We will also become informed very shortly of the procedures but anticipate
it to include development and submission of Compliance Test Suites
(already partly covered by Simple-V unit tests, kindly funded by NLnet)
as well as ongoing work on the Simulator.

# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?

A lot! 

# Requested Amount    

EUR 100,000.

# Explain what the requested budget will be used for? 

* Design and fabrication of Libre/Open Hardware Dual FPGA Carrier
  boards (most likely accepting OrangeCrab as a module)
* Porting of both LibreBMC and OpenBMC to the FPGA Board
* Implementation of *server* side LPC (client-side already exists)
* Verilator simulation of both client and server side LPC
  and testing of the two simulations back-to-back

# Compare your own project with existing or historical efforts.


## What are significant technical challenges you expect to solve during the project, if any?



## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?


# Extra info to be submitted

* TODO URLs etc