# OPF ISA WG External RFC ls005 v1: XLEN

* RFC Author: Luke Kenneth Casson Leighton.
* RFC Contributors/Ideas: Jacob Lifshay, Toshaan Bharvani
* Funded by NLnet under the NGI Zero Entrust EU Horizon Europe Grant 101069594

**URLs**:

* <https://libre-soc.org/openpower/sv/rfc/ls005/>
* <https://bugs.libre-soc.org/show_bug.cgi?id=663>
* <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isa;hb=HEAD>
* <https://git.openpower.foundation/isa/PowerISA/issues/104>

**Severity**: Major

**Status**: New

**Date**: 22 Dec 2022

**Target**: v3.2B

**Source**: v3.0B

**Books and Section affected**:

```
    Everything (in a consistent, regular and systematic fashion)
```

**Summary**

```
    Exactly as is already done in RISC-V, convert the entire use of 64-bit hard-coding to "XLEN".
    Exactly as is in RISC-V, options then include PowerISA-32, PowerISA-64 and PowerISA-128.
    Unlike in RISC-V, the concept of PowerISA-16 and PowerISA-8 is also floated, for Embedded,
    AI, Edge, Processing-in-Memory, Distributed Computing and other purposes.
```

**Submitter**: Luke Leighton (Libre-SOC)

**Requester**: Libre-SOC

**Impact on processor**:

```
    Entirely new processors, entirely new markets.
```

**Impact on software**:

```
    Massive but regular, consistent, and systematic.
```

**Keywords**:

```
    XLEN
```

**Motivation**

The Power ISA is far too massive, making it wholly unsuited for Embedded
markets and adversely impacting its reach and potential.  The RISC paradigm
it is based on has gone too far into PackedSIMD (128-bit).  Fixing this is
relatively and conceptually straightforward: allow 32-bit and even 16-bit
and 8-bit implementations, and use the opportunity to allow future Scalar
128-bit implementations in the exact same strategic way that RISC-V has RV128.

Register files are redefined to XLEN width but are permitted to "group"
registers together to create 16-bit, 32-bit and 64-bit addresses.
In this way, the limitations of what would otherwise restrict the usefulness
of a severely-targetted application-specific processor may be overcome in
order to make it still possible to (at reduced performance) still run
general-purpose applications.
AI application-specific processing or other Processing-In-Memory or other
specialist design therefore may for example focus a balance
of raw computing power heavily onto 8-bit or 16-bit computation, but still
gain the benefit of the Power ISA and everything it brings.  Contrast
this with the more "normal" approach of creating heavily-focussed
specialist "AI" Engines incapable of Turing-completeness and the benefits
are clear.

Note: SVP64 **requires** this change as a 100% critical dependency.
SIMD back-end ALUs process Vectors of "Elements" at 8, 16 and 32-bit (and
64-bit), read from, processed, and returned to, the standard **Scalar**
Register Files, with byte-level write-enable lines.

**Changes**

For all pseudocode right across the board in all Scalar operations, replace
hard-coded "64" with "XLEN".  **This work is already underway as sponsored
by NLnet in the Libre-SOC Power ISA Pseudocode**.  The default is obviously
recommended to be "XLEN=64" in order to create zero disruption.

Definitions of the Register File(s) for GPR and FPR are then changed to be
"XLEN" wide.  However, for Embedded purposes (XLEN=32/16/8), an SPR controls
whether (and how many) sequentially-grouped registers are taken together to
create 16-bit, 32-bit and 64-bit addresses (depending on application need).
GPR is obvious, FPR is quirky.  SVP64 redefines FP ops (those not ending in "s")
to be "full width" and all ops ending in "s" to be "half of
the FP width".

* XLEN=64 keeps FPR "full width" exactly as presently defined, and
  "half width" exactly as presently defined.
* XLEN=32 overrides FPR "full width" operations to
  full FP32, and "half width" to be "FP16 stored in an FP32"
* XLEN=16 redefines FPR "full width" operations to full [IEEE FP16](https://en.wikipedia.org/wiki/Half-precision_floating-point_format) and leaves
  "half width" UNDEFINED (there is no IEEE FP8).
* XLEN=8 redefines FPR "full width" operations to [BF16 (bfloat16)](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) and leaves
  "half width" UNDEFINED[^1]. Note this means FPRs are 16 bits, not 8.

[^1]: BF8 is very rarely used, though it does exist as the MSB half of IEEE FP16

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