# RFC ls008 SVP64 Management instructions

[[!tag opf_rfc]]

**URLs**:

* <https://libre-soc.org/openpower/sv/>
* <https://libre-soc.org/openpower/sv/rfc/ls008/>
* <https://bugs.libre-soc.org/show_bug.cgi?id=1040>
* <https://git.openpower.foundation/isa/PowerISA/issues/87>

**Severity**: Major

**Status**: New

**Date**: 24 Mar 2023

**Target**: v3.2B

**Source**: v3.0B

**Books and Section affected**:

```
    Book I, new Scalar Chapter.  (Or, new Book on "Zero-Overhead Loop Subsystem")
    Appendix E Power ISA sorted by opcode
    Appendix F Power ISA sorted by version
    Appendix G Power ISA sorted by Compliancy Subset
    Appendix H Power ISA sorted by mnemonic
```

**Summary**

```
    Instructions added
    setvl    - Cray-style "Set Vector Length" instruction
    svstep   - Vertical-First Mode explicit Step and Status
    svremap  - Re-Mapping of Register Element Offsets
    svindex  - General-purpose setting of SHAPEs to be re-mapped
    svshape  - Hardware-level setting of SHAPEs for element re-mapping
    svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
```

**Submitter**: Luke Leighton (Libre-SOC)

**Requester**: Libre-SOC

**Impact on processor**:

```
    Addition of six new "Zero-Overhead-Loop-Control" DSP-style Vector-style
    Management Instructions which can be implemented extremely efficiently
    and effectively by inserting an additional phase between Decode and Issue.
    More complex designs are NOT adversely impacted and in fact greatly benefit
    whilst still retaining an obvious linear sequential execution programming model.
```

**Impact on software**:

```
    Requires support for new instructions in assembler, debuggers,
    and related tools.
```

**Keywords**:

```
    Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control,
    Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model
```

**Motivation**

TODO

**Notes and Observations**:

1. TODO

**Changes**

Add the following entries to:

* the Appendices of Book I
* Instructions of Book I as a new Section
* SVL-Form of Book I Section 1.6.1.6 and 1.6.2

----------------

\newpage{}

# svstep: Vertical-First Stepping and status reporting

SVL-Form

* svstep RT,SVi,vf (Rc=0)
* svstep. RT,SVi,vf (Rc=1)

| 0-5|6-10|11.15|16..22| 23-25    | 26-30 |31|   Form   |
|----|----|-----|------|----------|-------|--|--------- |
|PO  | RT | /   | SVi  |  / / vf  | XO    |Rc| SVL-Form |

Pseudo-code:

```
    if SVi[3:4] = 0b11 then
        # store subvl, pack and unpack in SVSTATE
        SVSTATE[53] <- SVi[5]
        SVSTATE[54] <- SVi[6]
        RT <- [0]*62 || SVSTATE[53:54]
    else
        step <- SVSTATE_NEXT(SVi, vf)
        RT <- [0]*57 || step

```

Special Registers Altered:

    CR0                     (if Rc=1)


-------------

\newpage{}

# SVL-Form

Add the following to Book I, 1.6.1, SVL-Form

```
    |0     |6    |11    |16   |23 |24 |25 |26    |31 |
    | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
    | PO   |  RT | /    | SVi |/  |/  |vf |   XO |Rc |
```

* Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
* Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
* Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
* Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2

Add the following to Book I, 1.6.2

```

```


# Appendices

    Appendix E Power ISA sorted by opcode
    Appendix F Power ISA sorted by version
    Appendix G Power ISA sorted by Compliancy Subset
    Appendix H Power ISA sorted by mnemonic

| Form | Book | Page | Version | mnemonic | Description |
|------|------|------|---------|----------|-------------|
| SVL  | I    | #    | 3.0B    | svstep   | Vertical-First Stepping and status reporting |