# RFC ls008 SVP64 Management instructions
[[!tag opf_rfc]]
**URLs**:
*
*
*
*
**Severity**: Major
**Status**: New
**Date**: 24 Mar 2023
**Target**: v3.2B
**Source**: v3.0B
**Books and Section affected**:
```
Book I, new Scalar Chapter. (Or, new Book on "Zero-Overhead Loop Subsystem")
Appendix E Power ISA sorted by opcode
Appendix F Power ISA sorted by version
Appendix G Power ISA sorted by Compliancy Subset
Appendix H Power ISA sorted by mnemonic
```
**Summary**
```
Instructions added
setvl - Cray-style "Set Vector Length" instruction
svstep - Vertical-First Mode explicit Step and Status
svremap - Re-Mapping of Register Element Offsets
svindex - General-purpose setting of SHAPEs to be re-mapped
svshape - Hardware-level setting of SHAPEs for element re-mapping
svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
```
**Submitter**: Luke Leighton (Libre-SOC)
**Requester**: Libre-SOC
**Impact on processor**:
```
Addition of six new "Zero-Overhead-Loop-Control" DSP-style Vector-style
Management Instructions which can be implemented extremely efficiently
and effectively by inserting an additional phase between Decode and Issue.
More complex designs are NOT adversely impacted and in fact greatly benefit
whilst still retaining an obvious linear sequential execution programming model.
```
**Impact on software**:
```
Requires support for new instructions in assembler, debuggers,
and related tools.
```
**Keywords**:
```
Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control,
Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model
```
**Motivation**
TODO
**Notes and Observations**:
1. TODO
**Changes**
Add the following entries to:
* the Appendices of Book I
* Instructions of Book I as a new Section
* SVL-Form of Book I Section 1.6.1.6 and 1.6.2
----------------
\newpage{}
# svstep: Vertical-First Stepping and status reporting
SVL-Form
* svstep RT,SVi,vf (Rc=0)
* svstep. RT,SVi,vf (Rc=1)
| 0-5|6-10|11.15|16..22| 23-25 | 26-30 |31| Form |
|----|----|-----|------|----------|-------|--|--------- |
|PO | RT | / | SVi | / / vf | XO |Rc| SVL-Form |
Pseudo-code:
```
if SVi[3:4] = 0b11 then
# store subvl, pack and unpack in SVSTATE
SVSTATE[53] <- SVi[5]
SVSTATE[54] <- SVi[6]
RT <- [0]*62 || SVSTATE[53:54]
else
step <- SVSTATE_NEXT(SVi, vf)
RT <- [0]*57 || step
```
Special Registers Altered:
CR0 (if Rc=1)
-------------
\newpage{}
# setvl
SVL-Form
* setvl RT,RA,SVi,vf,vs,ms (Rc=0)
* setvl. RT,RA,SVi,vf,vs,ms (Rc=1)
Pseudo-code:
overflow <- 0b0
VLimm <- SVi + 1
# set or get MVL
if ms = 1 then MVL <- VLimm[0:6]
else MVL <- SVSTATE[0:6]
# set or get VL
if vs = 0 then VL <- SVSTATE[7:13]
else if _RA != 0 then
if (RA) >u 0b1111111 then
VL <- 0b1111111
overflow <- 0b1
else VL <- (RA)[57:63]
else if _RT = 0 then VL <- VLimm[0:6]
else if CTR >u 0b1111111 then
VL <- 0b1111111
overflow <- 0b1
else VL <- CTR[57:63]
# limit VL to within MVL
if VL >u MVL then
overflow <- 0b1
VL <- MVL
SVSTATE[0:6] <- MVL
SVSTATE[7:13] <- VL
if _RT != 0 then
GPR(_RT) <- [0]*57 || VL
if ((¬vs) & ¬(ms)) = 0 then
# set requested Vertical-First mode, clear persist
SVSTATE[63] <- vf
SVSTATE[62] <- 0b0
Special Registers Altered:
CR0 (if Rc=1)
-------------
\newpage{}
# SVSTATE SPR
The format of the SVSTATE SPR is as follows:
| Field | Name | Description |
| ----- | -------- | --------------------- |
| 0:6 | maxvl | Max Vector Length |
| 7:13 | vl | Vector Length |
| 14:20 | srcstep | for srcstep = 0..VL-1 |
| 21:27 | dststep | for dststep = 0..VL-1 |
| 28:29 | dsubstep | for substep = 0..SUBVL-1 |
| 30:31 | ssubstep | for substep = 0..SUBVL-1 |
| 32:33 | mi0 | REMAP RA SVSHAPE0-3 |
| 34:35 | mi1 | REMAP RB SVSHAPE0-3 |
| 36:37 | mi2 | REMAP RC SVSHAPE0-3 |
| 38:39 | mo0 | REMAP RT SVSHAPE0-3 |
| 40:41 | mo1 | REMAP EA SVSHAPE0-3 |
| 42:46 | SVme | REMAP enable (RA-RT) |
| 47:52 | rsvd | reserved |
| 53 | pack | PACK (srcstrp reorder) |
| 54 | unpack | UNPACK (dststep order) |
| 55:61 | hphint | Horizontal Hint |
| 62 | RMpst | REMAP persistence |
| 63 | vfirst | Vertical First mode |
Notes:
* The entries are truncated to be within range. Attempts to set VL to
greater than MAXVL will truncate VL.
* Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
than 64 is reserved and will cause an illegal instruction trap.
-------------
\newpage{}
# SVL-Form
Add the following to Book I, 1.6.1, SVL-Form
```
|0 |6 |11 |16 |23 |24 |25 |26 |31 |
| PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
| PO | RT | / | SVi |/ |/ |vf | XO |Rc |
```
* Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
* Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
* Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
* Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2
Add the following to Book I, 1.6.2
```
ms (23)
Field used in Simple-V to specify whether MVL (maxvl in the SVSTATE SPR)
is to be set
Formats: SVL
vf (25)
Field used in Simple-V to specify whether "Vertical" Mode is set
(vfirst in the SVSTATE SPR)
Formats: SVL
vs (24)
Field used in Simple-V to specify whether VL (vl in the SVSTATE SPR) is to be set
Formats: SVL
SVi (16:22)
Simple-V immediate field for setting VL or MVL (vl, maxvl in the SVSTATE SPR)
Formats: SVL
```
# Appendices
Appendix E Power ISA sorted by opcode
Appendix F Power ISA sorted by version
Appendix G Power ISA sorted by Compliancy Subset
Appendix H Power ISA sorted by mnemonic
| Form | Book | Page | Version | mnemonic | Description |
|------|------|------|---------|----------|-------------|
| SVL | I | # | 3.0B | svstep | Vertical-First Stepping and status reporting |