# RGMII Gigabit Ethernet PHY

* <http://bugs.libre-riscv.org/show_bug.cgi?id=9>
* <https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/eth_mac_1g_rgmii.v>
* <https://github.com/pkerling/ethernet_mac> - doesn't do RGMII, does GMII.
* <https://github.com/enjoy-digital/liteeth> - MII RMII GMII RGMII PHY
* <https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py> - RMII in nmigen
* <https://github.com/HarryMakes/nmigen-stdio/blob/eth/nmigen_stdio/eth/rgmii.py>
 <https://git.m-labs.hk/M-Labs/HeavyX/commit/59d26d148d58d1b385ba935b6e0685d8d3e850c7>
* simulation verilator https://github.com/ZipCPU/xulalx25soc/blob/master/bench/cpp/sdramsim.cpp