# SDRAM

* <https://bitbucket.org/casl/c-class/src/3fba75dfbd0c64815eb8ec6dc965666812c44bae/src/peripherals/sdram/?at=master>
* <https://opencores.org/projects/sdr_ctrl>
* WIP <https://gitlab.com/jock_tanner/asceticore/-/blob/master/control.py#L24-31>